File:MLCC-Principle.svg|Construction of a multilayer ceramic chip capacitor (MLCC), 1 = Metallic electrodes, 2 = Dielectric ceramic, 3 = Connecting terminals File:Ceramic disc capacitor.png|Construction of a ceramic disc capacitor Ceramic capacitors are composed of a mixture of finely ground granules of paraelectric or ferroelectric materials, appropriately mixed with other materials to achieve the desired characteristics. From these powder mixtures, the ceramic is
sintered at high temperatures. The ceramic forms the dielectric and serves as a carrier for the metallic electrodes. The minimum thickness of the dielectric layer, which today (2013) for low voltage capacitors is in the size range of 0.5
micrometers The composition of the mixture and the size of the powder particles, as small as 10 nm, reflect the manufacturer's expertise. A thin ceramic foil is cast from a suspension of the powder with a suitable binder. Rolls of foil are cut into equal-sized sheets, which are screen printed with a metal paste layer, which will become the electrodes. In an automated process, these sheets are stacked in the required number of layers and solidified by pressure. Besides the relative permittivity, the size and number of layers determines the later capacitance value. The electrodes are stacked in an alternating arrangement slightly offset from the adjoining layers so that they each can later be connected on the offset side, one left, one right. The layered stack is pressed and then cut into individual components. High mechanical precision is required, for example, to produce a 500 or more layer stack of size "0201" (0.5 mm × 0.3 mm). After cutting, the binder is burnt out of the stack. This is followed by sintering at temperatures between , producing the final, mainly crystalline, structure. This burning process creates the desired dielectric properties. Burning is followed by cleaning and then metallization of both end surfaces. Through the metallization, the ends and the inner
electrodes are connected in parallel and the capacitor gets its terminals. Finally, each capacitor is electrically tested to ensure functionality and adequate performance, and packaged in a tape reel.
Miniaturizing The capacitance formula (
C) of a MLCC capacitor is based on the formula for a plate capacitor enhanced with the number of layers: C=\varepsilon \cdot { {n \cdot A} \over {d} } where
ε stands for dielectric
permittivity;
A for electrode surface area; n for the number of layers; and
d for the distance between the electrodes. A thinner dielectric or a larger electrode area each increase the
capacitance value, as will a dielectric material of higher permittivity. With the progressive miniaturization of
digital electronics in recent decades, the components on the periphery of the integrated logic circuits have been scaled down as well. Shrinking an MLCC involves reducing the dielectric thickness and increasing the number of layers. Both options require huge efforts and are connected with a lot of expertise. In 1995 the minimum thickness of the dielectric was 4 μm. By 2005 some manufacturers produced MLCC chips with layer thicknesses of 1 μm. , the minimum thickness is about 0.5 μm. The size reduction of these capacitors is achieved reducing powder grain size, the assumption to make the ceramic layers thinner. In addition, the manufacturing process became more precisely controlled, so that more and more layers can be stacked. Between 1995 and 2005, the capacitance of a Y5V MLCC capacitor of size 1206 was increased from 4.7 μF to 100 μF. Meanwhile, (2013) a lot of producers can deliver class 2 MLCC capacitors with a capacitance value of 100 μF in the chip-size 0805.
MLCC case sizes MLCCs don't have leads, and as a result they are usually smaller than their counterparts with leads. They don't require through-hole access in a PCB to mount and are designed to be handled by machines rather than by humans. As a result, surface-mount components like MLCCs are typically cheaper. MLCCs are manufactured in standardized shapes and sizes for comparable handling. Because the early standardization was dominated by American EIA standards the dimensions of the MLCC chips were standardized by EIA in units of inches. A rectangular chip with the dimensions of 0.06-inch length and 0.03-inch width is coded as "0603". This code is international and in common use.
JEDEC (IEC/EN), devised a second, metric code. The EIA code and the metric equivalent of the common sizes of multilayer ceramic chip capacitors, and the dimensions in mm are shown in the following table. Missing from the table is the measure of the height "H". This is generally not listed, because the height of MLCC chips depends on the number of layers and thus on the capacitance. Normally, however, the height H does not exceed the width W.
NME and BME metallization File:MLCC-BME-NME-engl.png|Structure of the electrodes and the NME respectively BME metallization of the terminals of MLCC cchips File:MLCC-BME-NME-Kap-Spg-Kurve-engl.svg|Influence of the NME respectively BME metallization for class 2 X7R MLCC chips on the voltage dependence of capacitance. Originally, MLCC electrodes were constructed out of noble metals such as silver and palladium which can withstand high sintering temperatures of without readily oxidizing. These
noble metal electrode (NME) capacitors offered very good electrical properties. However, a surge in prices of noble metals in the late 1990s greatly increased manufacturing costs; these pressures resulted in the development of capacitors that used cheaper metals like
copper and
nickel. These
base metal electrode (BME) capacitors possessed poorer electrical characteristics; exhibiting greater shrinkage of capacitance at higher voltages and increased loss factor. The disadvantages of BME were deemed acceptable for class 2 capacitors, which are primarily used in accuracy-insensitive, low-cost applications such as power supplies. NME still sees use in class 1 capacitors where conformance to specifications are critical and cost is less of a concern.
MLCC capacitance ranges Capacitance of MLCC chips depends on the dielectric, the size and the required voltage (rated voltage). Capacitance values start at about 1pF. The maximum capacitance value is determined by the production technique. For X7R that is 47 μF, for Y5V: 100 μF. The picture right shows the maximum capacitance for class 1 and class 2 multilayer ceramic chip capacitors. The following two tables, for ceramics NP0/C0G and X7R each, list for each common case size the maximum available capacitance value and rated voltage of the leading manufacturers Murata, TDK, KEMET, AVX. (Status April 2017)
Low-ESL styles File:MLCC-Standard-Layout.svg|Standard MLCC chip design File:MLCC-Low-ESL-Layout.svg|Low-ESL design of an MLCC chip File:MLCC-Low-ESL-Array-Layout.svg|MLCC chip array In the region of its
resonance frequency, a capacitor has the best decoupling properties for noise or
electromagnetic interference. The resonance frequency of a capacitor is determined by the
inductance of the component. The inductive parts of a capacitor are summarized in the equivalent series inductance, or ESL. (Note that L is the electrical symbol for inductance.) The smaller the inductance, the higher the resonance frequency. Because, especially in
digital signal processing, switching frequencies have continued to rise, the demand for high frequency decoupling or filter capacitors increases. With a simple design change the ESL of an MLCC chip can be reduced. Therefore, the stacked electrodes are connected on the longitudinal side with the connecting terminations. This reduces the distance that the charge carriers flow over the electrodes, which reduces inductance of the component. For example, an 0.1 μF X7R MLCC in a 0805 package resonates at 16 MHz. The same capacitor with leads on its long sides (i.e. an
0508) has a resonance frequency of 22 MHz. Another possibility is to form the device as an array of capacitors. Here, several individual capacitors are built in a common housing. Connecting them in parallel, the resulting ESL as well as ESR values of the components are reduced.
X2Y decoupling capacitor File:Capacitors x2y.jpg|X2Y decoupling capacitors with different case sizes File:MLCC-X2Y-Decoupling-Capacitor.png|Inner construction of a X2Y capacitor File:MLCC-X2Y-Circuit.png|Circuit diagram of a X2Y capacitor in a decoupling circuit A standard multi-layer ceramic capacitor has many opposing electrode layers stacked inside connected with two outer terminations. The X2Y ceramic chip capacitor however is a 4 terminal chip device. It is constructed like a standard two-terminal MLCC out of the stacked ceramic layers with an additional third set of shield electrodes incorporated in the chip. These shield electrodes surround each existing electrode within the stack of the capacitor plates and are low ohmic contacted with two additional side terminations across to the capacitor terminations. The X2Y construction results in a three-node capacitive circuit that provides simultaneous line-to-line and line-to-ground filtering. Capable of replacing 2 or more conventional devices, the X2Y ceramic capacitors are ideal for high frequency filtering or noise suppression of supply voltages in digital circuits, and can prove invaluable in meeting stringent
EMC demands in dc motors, in automotive, audio, sensor and other applications. The X2Y footprint results in lower mounted inductance. This is particularly of interest for use in high-speed digital circuits with clock rates of several 100 MHz and upwards. There the decoupling of the individual supply voltages on the circuit board is difficult to realize due to parasitic inductances of the supply lines. A standard solution with conventional ceramic capacitors requires the parallel use of many conventional MLCC chips with different capacitance values. Here X2Y capacitors are able to replace up to five equal-sized ceramic capacitors on the PCB. However, this particular type of ceramic capacitor is patented, so these components are still comparatively expensive. An alternative to X2Y capacitors may be a three-terminal capacitor.
Mechanical susceptibility Ceramics are brittle, and MLCC chips
surface-mount soldered to a circuit board are often vulnerable to cracking from
thermal expansion or mechanical stresses like
depanelization, more so than leaded
through-hole components. The cracks can come from automated machine assembly line, or from high current in the circuit. Vibration and shock forces on the circuit board are more or less transmitted undampened to the MLCC and its solder joints; excessive force may cause the capacitor to crack (
flex crack). Excess solder in the joints are undesirable as they may magnify the forces that the capacitor is subject to. File:SMD-chip-soldering.svg|Correct mounted and soldered MLCC chip on a PCB File:MLCC-Schliffbild-mit-Bruch.png|Micrograph of broken ceramic in a MLCC chip File:MLCC-Flexure-Test engl.svg|Simplified figure of a bending test for soldered MLCC The capability of MLCC chips to withstand mechanical stress is tested by a so-called substrate bending test, where a PCB with a soldered MLCC is bent by a punch by 1 to 3 mm. Failure occurs if the MLCC becomes a
short-circuit or significantly changes in capacitance. Bending strengths of MLCC chips differ by the ceramic material, the size of the chip, and the physical construction of the capacitors. Without special mitigation, NP0/C0G class 1 ceramic MLCC chips reach a typical bending strength of 2 mm while larger types of X7R, Y5V class 2 ceramic chips achieved only a bending strength of approximately 1 mm. Smaller chips, such as the size of 0402, reached in all types of ceramics larger bending strength values. With special design features, particularly at the electrodes and terminations, the bending strength can be improved. For example, an internal short circuit arises by the contact of two electrodes with opposite polarity, which will be produced at the break of the ceramic in the region of the terminations. This can be prevented when the overlap surfaces of the electrodes are reduced. This is achieved e.g. by an "
Open Mode Design" (OMD). Here a break in the region of the terminations only reduce the capacitance value a little bit (AVX, KEMET). File:MLCC-Standard-Crack.svg|Standard MLCC chip, short circuit possible if ceramic breaks due to mechanical stress File:MLCC-Fail-Open-Crack.svg|„Open-Mode-Design" MLCC chip, a break only reduces the capacitance value File:MLCC-Floating-Electrode-Crack.svg|"Floating-Electrode-Design"-MLCC, a break only reduces the capacitance value File:MLCC-FlexTerm-Crack.svg|"Flex-Termination" - MLCC chips, a flexible contact layer prevents breaking of the ceramic. With a similar construction called "Floating Electrode Design" (FED) or "Multi-layer Serial Capacitors" (MLSC), also, only capacitance reduction results if parts of the capacitor body break. This construction works with floating electrodes without any conductive connection to the termination. A break doesn't lead to a short, only to capacitance reduction. However, both structures lead to larger designs with respect to a standard MLCC version with the same capacitance value. The same volume with respect to standard MLCCs is achieved by the introduction of a flexible intermediate layer of a conductive polymer between the electrodes and the termination called "Flexible Terminations" (FT-Cap) or "Soft Terminations". In this construction, the rigid metallic soldering connection can move against the flexible polymer layer, and thus can absorb the bending forces, without resulting in a break in the ceramic. Some automotive capacitors are specified to adhere to
AEC-Q200 and/or
VW 80808.
RFI/EMI suppression with X- and Y capacitors Suppression capacitors are effective interference reduction components because their electrical
impedance decreases with increasing frequency, such that at higher frequencies they appear as short circuits to high-frequency electrical noise and transients between the lines, or to ground. They therefore prevent equipment and machinery (including motors, inverters, and electronic ballasts, as well as solid-state relay snubbers and spark quenchers) from sending and receiving electromagnetic and radio frequency interference as well as transients in across-the-line (X capacitors) and line-to-ground (Y capacitors) connections. X capacitors effectively absorb symmetrical, balanced, or differential interference. Y capacitors are connected in a line bypass between a line phase and a point of zero potential, to absorb asymmetrical, unbalanced, or common-mode interference. File:Safety caps-Appliance Class I.svg|Appliance Class I capacitor connection File:Safety caps-Appliance Class II.svg|Appliance Class II capacitor connection EMI/RFI suppression capacitors are designed so that any remaining interference or electrical noise does not exceed the limits of EMC directive EN 50081. Suppression components are connected directly to mains voltage for 10 to 20 years or more and are therefore exposed to potentially damaging overvoltages and transients. For this reason, suppression capacitors must comply with the safety and non-flammability requirements of international safety standards such as • Europe: EN 60384-14, • USA: UL 1414, UL 1283 • Canada: CSA C22.2, No.1, CSA C22.2, No.8 • China: CQC (GB/T 14472-1998) RFI capacitors that fulfill all specified requirements are imprinted with the
certification mark of various national safety standards agencies. For power line applications, special requirements are placed on the non-flammability of the coating and the epoxy resin impregnating or coating the capacitor body. To receive safety approvals, X and Y powerline-rated capacitors are
destructively tested to the point of failure. Even when exposed to large overvoltage surges, these safety-rated capacitors must fail in a
fail-safe manner that does not endanger personnel or property. most ceramic capacitors used for EMI/RFI suppression were leaded ones for through-hole mounting on a PCB, the surface-mount technique is becoming more and more important. For this reason, in recent years a lot of MLCC chips for EMI/RFI suppression from different manufacturers have received approvals and fulfill all requirements given in the applicable standards.
Ceramic power capacitors File:Kerko-HV-Scheibenkondensator.png|Doorknob style high voltage ceramic capacitor File:Kerko-Leistung-P1080451b.jpg|Disc style power ceramic capacitor File:Kerko-Leistung-P1080446b.jpg|Tubular or pot style power ceramic capacitor Although the materials used for large power ceramic capacitors mostly are very similar to those used for smaller ones, ceramic capacitors with high to very high power or voltage ratings for applications in power systems, transmitters and electrical installations are often classified separately, for historical reasons. The standardization of ceramic capacitors for lower power is oriented toward electrical and mechanical parameters as components for use in electronic equipment. The standardization of power capacitors, contrary to that, is strongly focused on protecting personnel and equipment, given by the local regulating authority. As modern electronic equipment gained the ability to handle power levels that were previously the exclusive domain of "electrical power" components, the distinction between the "electronic" and "electrical" power ratings has become less distinct. In the past, the boundary between these two families was approximately at a reactive power of 200 volt-amps, but modern power electronics can handle increasing amounts of power. Power ceramic capacitors are mostly specified for much higher than 200 volt-amps. The great plasticity of ceramic raw material and the high dielectric strength of ceramics deliver solutions for many applications and are the reasons for the enormous diversity of styles within the family of power ceramic capacitors. These power capacitors have been on the market for decades. They are produced according to the requirements as class 1 power ceramic capacitors with high stability and low losses or class 2 power ceramic capacitors with high volumetric efficiency. Class 1 power ceramic capacitors are used for
resonant circuit application in
transmitter stations. Class 2 power ceramic capacitors are used for
circuit breakers, for
power distribution lines, for high voltage
power supplies in laser-applications, for
induction furnaces and in
voltage-doubling circuits. Power ceramic capacitors can be supplied with high rated voltages in the range of 2 kV up to 100 kV. The dimensions of these power ceramic capacitors can be very large. At high power applications the losses of these capacitors can generate a lot of heat. For this reason some special styles of power ceramic capacitors have pipes for water-cooling. ==Electrical characteristics==