CDNA (microarchitecture)

The CDNA family consists of one die, named Arcturus. The die is 750 square millimetres, contains 25.6 billion transistors and is manufactured on TSMC's N7 node. The Arcturus die possesses 120 compute units and a 4096-bit memory bus, connected to four HBM2 placements, giving the die 32 GB of memory, and just over 1200 GB/s of memory bandwidth. Compared to its predecessor, CDNA has removed all hardware related to graphics acceleration. This removal includes but is not limited to: graphics caches, tessellation hardware, render output units (ROPs), and the display engine. CDNA retains the VCN media engine for HEVC, H.264, and VP9 decoding. CDNA has also added dedicated matrix compute hardware, similar to those added in Nvidia's Volta Architecture. Architecture The 120 compute units (CUs) are organized into 4 asynchronous compute engines (ACEs), each ACE maintaining its own independent command execution and dispatch. At the CU level, CDNA compute units are organized similarly to GCN units. Each CU contains four SIMD16, that each execute their 64-thread wavefront (Wave64) over four cycles. Memory system CDNA has a 20% clock bump for the HBM, resulting in a roughly 200 GB/s bandwidth increase vs. Vega 20 (GCN 5.0). The die has a shared 4 MB L2 cache that puts out 2 KB per clock to the CUs. At the CU level, each CU has its own L1 cache, a local data store (LDS) with 64 KB per CU and a 4 KB global data store (GDS), shared by all CUs. This GDS can be used to store control data, reduction operations or act as a small global shared surface. Experimental PIM implementation In October 2022, Samsung demonstrated a Processing-In-Memory (PIM) specialized version of the MI100. In December 2022 Samsung showed off a cluster of 96 modified MI100s, boasting large increases in processing throughput for various workloads and significant reduction in power consumption. Changes from GCN The individual compute units remain highly similar to GCN but with the addition of 4 matrix units per CU. Support for more datatypes were added, with BF16, INT8 and INT4 being added. For an extensive list of operations utilizing the matrix units and new datatypes, please reference the CDNA ISA Reference Guide. Products == CDNA 2 ==

Like CDNA, CDNA 2 also consists of one die, named Aldebaran. This die is estimated to be 790 square millimetres, and contains 28 billion transistors while being manufactured on TSMC's N6 node. The Aldebaran die contains only 112 compute units, a 6.67% decrease from Arcturus. Like the previous generation, this die contains a 4096-bit memory bus, now using HBM2e with a doubling in capacity, up to 64 GB. The largest change in CDNA 2 is the ability for two dies to be placed on the same package. The MI250X consists of 2 Aldebaran dies, 220 CUs (110 per die) and 128 GB of HBM2e. These dies are connected with 4 Infinity Fabric links, and addressed as independent GPUs by the host system. Each die contains 8 Infinity Fabric links, each physically implemented with a 16-lane Infinity Link. When paired with an AMD processor, this will act as Infinity Fabric. if paired with any other x86 processor, this will fallback to 16 lanes of PCIe 4.0. INT32 multiply is also now executed at full rate like INT32 add, unlike the quarter-rate seen in GCN. Additionally support for packed FP32 operations were added, with opcodes like and . Packed FP32 operations can enable up to 2x throughput, but do require code modification (at minimum, recompilation). As with CDNA, for further information on CDNA 2 operations, please reference the CDNA 2 ISA Reference Guide. Products == CDNA 3 ==

Unlike its predecessors, CDNA 3 consists of multiple dies, used in a multi-chip system, similar to AMD's Zen 2, 3, 4 and 5 line of products. The MI300 package is comparatively massive, with nine chiplets produced on 5 nm, placed on top of four 6 nm chiplets. This is all combined with 128 GB of HBM3, using eight HBM placements. This package contains an estimated 146 billion transistors. It comes in the form of the Instinct MI300X and MI300A, the latter being an APU. These products were launched on December 6, 2023. The MI300X consists of 8 accelerator complex dies (XCDs) and 4 IO dies (IODs). The MI300A consists of 6 XCDs, 3 core complex dies (CCDs) with 8 Zen 4 cores each running at 3.7 GHz, and 4 IODs. Several MI300As can be used in the same system; for example, Gigabyte makes a quad-socket motherboard intended for four such APUs. Products == CDNA 4 ==

AMD announced the plans for MI350X and MI355X at Advancing AI 2025. The new models come in two forms: the single GPU in the OCP Accelerator Module (OAM) form factor and a water-cooled octo-GPU "platform" designed to fit onto a rack. Both are designed with the UBB (OCP universal baseboard) in mind. == See also ==