Zen 2 is a significant departure from the physical design paradigm of AMD's previous Zen architectures,
Zen and
Zen+. Zen 2 moves to a
multi-chip module design where the
I/O components of the CPU are laid out on its own
die which is separate from the dies containing processor cores, which are also called chiplets in this context. This separation has benefits in scalability and manufacturability. As physical interfaces don't scale very well with shrinks in
process technology, their separation into a different die allows these components to be manufactured using a larger, more mature process node than the CPU dies. The CPU dies (referred to by AMD as or CCDs), now more compact due to the move of I/O components onto another die, can be manufactured using a smaller process with fewer
manufacturing defects than a larger die would exhibit (since the chances of a die having a defect increases with device (die) size) while also allowing for more dies per wafer. In addition, the central I/O die can service multiple chiplets, making it easier to construct processors with a large number of cores. With Zen 2, each CPU chiplet houses 8 CPU cores, arranged in 2 (CCXs), each of 4 CPU cores. These chiplets are manufactured using
TSMC's
7 nanometer MOSFET node and are about 74 to 80 mm2 in size. The amount of
L3 cache has been doubled to 32 MB, with each CCX in the chiplet now having access to 16 MB of L3 compared to the 8 MB of Zen and Zen+.
AVX2 performance is greatly improved by an increase in execution unit width from 128-bit to 256-bit. There are multiple variants of the I/O die: one manufactured on
GlobalFoundries 14 nanometer process, and another manufactured using the same company's
12 nanometer process. The 14 nanometer dies have more features and are used for the EPYC Rome processors, whereas the 12 nm versions are used for consumer processors. AMD's Zen 2 architecture can deliver higher performance at a lower power consumption than Intel's
Cascade Lake architecture, with an example being the AMD Ryzen Threadripper 3970X running with a TDP of 140W in ECO mode delivering higher performance than the Intel Core i9-10980XE running with a TDP of 165W.
New features • Some new
instruction set extensions: WBNOINVD, CLWB, RDPID, RDPRU, MCOMMIT. Each instruction uses its own
CPUID bit. • Hardware mitigations against the Spectre V4 speculative store bypass vulnerability. • Zero-latency memory mirroring optimization (undocumented). • Doubled width of the execution units and load store units (from 128-bit to 256-bit) in the floating point coprocessor and significant further throughput enhancements in the multiplication execution unit. This allows the FPU to perform single-cycle AVX2 calculations. • Introduced CPPC power management. == Feature tables ==