Overview Compared to DDR2 memory, DDR3 memory uses less power. Some manufacturers further propose using
"dual-gate" transistors to reduce
leakage of current. According to
JEDEC, 1.575 volts should be considered the absolute maximum when memory stability is the foremost consideration, such as in servers or other mission-critical devices. In addition, JEDEC states that memory modules must withstand up to 1.80 volts before incurring permanent damage, although they are not required to function correctly at that level. In February 2005,
Samsung demonstrated the first DDR3 memory prototype, with a capacity of 512
Mb and a bandwidth of 1.066
Gbps. Products in the form of motherboards appeared on the market in June 2007 based on
Intel's
P35 "Bearlake" chipset with DIMMs at bandwidths up to DDR3-1600 (PC3-12800). The
Intel Core i7, released in November 2008, connects directly to memory rather than via a chipset. The Core i7, i5 & i3 CPUs initially supported only DDR3.
AMD's
socket AM3 Phenom II X4 processors, released in February 2009, were their first to support DDR3 (while still supporting DDR2 for backwards compatibility).
Dual-inline memory modules DDR3
dual-inline memory modules (DIMMs) have 240 pins and are electrically incompatible with DDR2. A key notch—located differently in DDR2 and DDR3 DIMMs—prevents accidentally interchanging them. Not only are they keyed differently, but DDR2 has rounded notches on the side and the DDR3 modules have square notches on the side. DDR3
SO-DIMMs have 204 pins. For the
Skylake microarchitecture, Intel has also designed a SO-DIMM package named
UniDIMM, which can use either DDR3 or DDR4 chips. The CPU's integrated memory controller can then work with either. The purpose of UniDIMMs is to handle the transition from DDR3 to DDR4, where pricing and availability may make it desirable to switch RAM type. UniDIMMs have the same dimensions and number of pins as regular DDR4 SO-DIMMs, but the notch is placed differently to avoid accidentally using in an incompatible DDR4 SO-DIMM socket.
Latencies DDR3 latencies are numerically higher because the I/O bus
clock cycles by which they are measured are shorter; the actual time interval is similar to DDR2 latencies, around 10 ns. There is some improvement because DDR3 generally uses more recent manufacturing processes, but this is not directly caused by the change to DDR3. CAS latency (ns) = 1000 × CL (cycles) ÷ clock frequency (MHz) = 2000 × CL (cycles) ÷ transfer rate (MT/s) While the typical
latencies for a JEDEC DDR2-800 device were 5-5-5-15 (12.5 ns), some standard latencies for JEDEC DDR3 devices include 7-7-7-20 for DDR3-1066 (13.125 ns) and 8-8-8-24 for DDR3-1333 (12 ns). As with earlier memory generations, faster DDR3 memory became available after the release of the initial versions. DDR3-2000 memory with 9-9-9-28 latency (9 ns) was available in time to coincide with the Intel Core i7 release in late 2008, while later developments made DDR3-2400 widely available (with CL 9–12 cycles = 7.5–10 ns), and speeds up to DDR3-3200 available (with CL 13 cycles = 8.125 ns).
Power consumption Power consumption of individual SDRAM chips (or, by extension, DIMMs) varies based on many factors, including speed, type of usage, voltage, etc. Dell's Power Advisor calculates that 4 GB ECC DDR1333 RDIMMs use about 4 W each. By contrast, a more modern mainstream desktop-oriented part 8 GB, DDR3/1600 DIMM, is rated at 2.58 W, despite being significantly faster.
Modules • optional DDR3-xxx denotes data transfer rate, and describes DDR chips, whereas PC3-xxxx denotes theoretical bandwidth (with the last two digits truncated), and is used to describe assembled DIMMs. Bandwidth is calculated by taking transfers per second and multiplying by eight. This is because DDR3 memory modules transfer data on a bus that is 64 data bits wide, and since a byte comprises 8 bits, this equates to 8 bytes of data per transfer. With two transfers per cycle of a quadrupled
clock signal, a 64-
bit wide DDR3 module may achieve a transfer rate of up to 64 times the memory
clock speed. With data being transferred 64 bits at a time per memory module, DDR3 SDRAM gives a transfer rate of (memory clock rate) × 4 (for bus clock multiplier) × 2 (for data rate) × 64 (number of bits transferred) / 8 (number of bits in a byte). Thus with a memory clock frequency of 100 MHz, DDR3 SDRAM gives a maximum transfer rate of 6400
MB/s. The data rate (in
MT/s) is twice the I/O bus clock (in
MHz) due to the
double data rate of DDR memory. As explained above, the bandwidth in MB/s is the data rate multiplied by eight. CL –
CAS Latency clock cycles, between sending a column address to the memory and the beginning of the data in response – Clock cycles between row activate and reads/writes – Clock cycles between row precharge and activate Fractional frequencies are normally rounded down, but rounding up to 667 is common because of the exact number being 666 and rounding to the nearest whole number. Some manufacturers also round to a certain precision or round up instead. For example, PC3-10666 memory could be listed as PC3-10600 or PC3-10700.
Note: All items listed above are specified by
JEDEC as JESD79-3F.
Alternative naming: DDR3 modules are often incorrectly labeled with the prefix PC (instead of PC3), for marketing reasons, followed by the data-rate. Under this convention PC3-10600 is listed as PC1333.
Serial presence detect DDR3 memory utilizes
serial presence detect. Serial presence detect (SPD) is a standardized way to automatically access information about a
computer memory module, using a serial interface. It is typically used during the
power-on self-test for automatic configuration of memory modules.
Release 4 Release 4 of the DDR3
Serial Presence Detect (SPD) document (SPD4_01_02_11) adds support for Load Reduction DIMMs and also for 16b-SO-DIMMs and 32b-SO-DIMMs. JEDEC Solid State Technology Association announced the publication of Release 4 of the DDR3 Serial Presence Detect (SPD) document on September 1, 2011.
XMP extension Intel Corporation officially introduced the eXtreme Memory Profile (
XMP) Specification on March 23, 2007, to enable enthusiast performance extensions to the traditional JEDEC
SPD specifications for DDR3 SDRAM. ==Variants==