The Emotion Engine consists of eight separate "units", each performing a specific task, integrated onto the same
die. These units are: a CPU core, two
Vector Processing Units (VPU), a 10-channel
DMA unit, a
memory controller, and an
Image Processing Unit (IPU). There are three interfaces: an input output interface to the I/O processor, a graphics interface (GIF) to the graphics synthesizer, and a memory interface to the system memory. The CPU core is tightly coupled to the first VPU, VPU0. Together, they are responsible for executing game code and high-level modeling computations. The second VPU, VPU1, is dedicated to geometry-transformations and lighting and operates independently, parallel to the CPU core, controlled by
microcode. VPU0, when not utilized, can also be used for geometry-transformations.
Display lists generated by CPU/VPU0 and VPU1 are sent to the GIF, which prioritizes them before dispatching them to the
Graphics Synthesizer for rendering.
CPU core The CPU core is a MIPS R5900 two-way
superscalar in-order RISC processor based on the
R5000, which implements the
MIPS-III instruction set architecture (ISA) with a subset of MIPS-IV in addition to a custom instruction set developed by Sony which operated on 128-bit wide groups of either 32-bit, 16-bit, or 8-bit integers in
single instruction, multiple data (SIMD) fashion (e.g. four 32-bit integers could be added to four others using a single instruction). Instructions defined include: add, subtract, multiply, divide, min/max, shift, logical, leading-zero count, 128-bit load/store and 256-bit to 128-bit funnel shift in addition to some not described by Sony for competitive reasons. Contrary to some misconceptions, these SIMD capabilities did not amount to the processor being "128-bit", as neither the memory addresses nor the integers themselves were 128-bit, only the shared SIMD/integer registers. For comparison, 128-bit wide registers and SIMD instructions had been present in the 32-bit
x86 architecture since 1999, with the introduction of
SSE. However the internal data paths were 128-bit wide, and its processors were capable of operating on 4x32bit quantities in parallel in single registers. It has a 6-stage integer
pipeline and a 15-stage
floating-point (FP) pipeline. Its assortment of registers consists of 32 128-bit VLIW SIMD registers (naming/renaming), one 64-bit accumulator and two 64-bit general data registers, 8 16-bit fix function registers, 16 8-bit controller registers. The processor also has two 64-bit integer
arithmetic logic units (ALUs), a 128-bit
load–store unit (LSU), a Branch Execution Unit (BXU), and a 32-bit VU1
floating-point unit (FPU) coprocessor (which acted as a sync controller for the VPU0/VPU1) containing a MIPS base processor core with 32 64-bit FP registers and 15 32-bit integer registers. The ALUs are 64-bit, with a 32-bit FPU that isn't
IEEE 754 compliant. The custom instruction set 107 MMI (Multimedia Extensions) was implemented by grouping the two 64-bit integer ALUs. Both the integer and floating-point pipelines are six stages long. To feed the execution units with instructions and data, there is a 16 KB two-way set
associative instruction cache, an 8 KB two-way set associative non blocking data cache and a 16 KB
scratchpad RAM. Both the instruction and data caches are virtually indexed and physically tagged while the
scratchpad RAM exists in a separate memory space. A combined 48 double entry instruction and data
translation lookaside buffer is provided for translating
virtual addresses.
Branch prediction is achieved by a 64-entry branch target address cache and a branch history table that is integrated into the instruction cache. The branch misprediction penalty is three cycles due to the short six stage pipeline.
Vector processing units The majority of the Emotion Engine's
floating point performance is provided by two
vector processing units (VPU), designated VPU0 and VPU1. These were essentially
DSPs tailored for 3D math, and the forerunner to
hardware vertex shader pipelines. Each VPU features 32
128-bit vector SIMD
registers (holding
4D vector data), 16 16-bit fixed-point registers, four floating point multiply-accumulate (FMAC) units, a floating point divide (FDIV) unit and a
local data memory. The data memory for VPU0 is 4 KB in size, while VPU1 features a 16 KB data memory. To achieve high bandwidth, the VPU's data memory is connected directly to the GIF, and both of the data memories can be read directly by the
DMA unit. A single vector instruction consists of four 32-bit
single-precision floating-point values which are distributed to the four single-precision (32-bit) FMAC units for processing. This scheme is similar to the
SSEx extensions by Intel. The FMAC units take four cycles to execute one instruction, but as the units have a six-stage
pipeline, they have a throughput of one instruction per cycle. The FDIV unit has a nine-stage pipeline and can execute one instruction every seven cycles.
Image Processing Unit (IPU) The IPU allowed
MPEG-2 compressed image decoding, allowing playback of DVDs and game
FMV. It also allowed vector quantization for 2D graphics data.
DMA, DRAM and Memory Management Unit (MMU) The memory management unit,
RDRAM controller and DMA controller handle memory access within the system. To provide communications between the Emotion Engine and the Input Output Processor (IOP), the input output interface interfaces a 32-bit wide, 37.5 MHz input output bus with a maximum theoretical bandwidth of 150 MB/s to the internal data bus. The interface provides enough bandwidth for the PCMCIA extension connector which was used for the network adapter with built-in P-ATA interface for faster data access and online functionality. An advantage of the high bandwidth was that it could be easily used to introduce hardware extensions like the Network Adapter with built-in IDE HDD support or other extensions to extend functionality and product lifecycle which can be seen as a competitive advantage. In newer variants (like the slim edition), the interface would however, offer vastly more bandwidth than what is required by the PlayStation's input output devices as the HDD support was removed and the PCMCIA connector design was abandoned in favor of a slimmer design. == Fabrication ==