Serial Peripheral Interface

Commonly, SPI has four logic signals. Variations may use different names or have different signals. : MOSI on a master outputs to MOSI on a slave. MISO on a slave outputs to MISO on a master. Each device internally uses a shift register for serial communication, which together forms an inter-chip circular buffer. To support multidrop bus, slave devices should use tri-state outputs so their MISO signal becomes high impedance (electrically disconnected) when the device is not selected. Slaves without tri-state outputs cannot share a MISO line with other slaves without using an external tri-state buffer. Data transmission s to form an inter-chip circular buffer To begin communication, the SPI master first selects the device it wants to communicate with by pulling its low. (The bar above indicates it is an active low signal, so a low voltage means "selected", while a high voltage means "not selected") If a waiting period is required, such as for an analog-to-digital conversion, the master must wait for at least that period of time before issuing clock cycles. During each SPI clock cycle, full-duplex transmission of a single bit occurs. The master sends a bit on the MOSI line while the slave sends a bit on the MISO line, and then each reads their corresponding incoming bit. This sequence is maintained even when only one-directional data transfer is intended. Transmission using a single slave involves one shift register in the master and one shift register in the slave, both of some given word size (e.g. 8 bits). The transmissions often consist of eight-bit words, but other word-sizes are also common, for example, sixteen-bit words for touch-screen controllers or audio codecs, such as the TSC2101 by Texas Instruments, or twelve-bit words for many digital-to-analog or analog-to-digital converters. Data is usually shifted out with the most-significant bit (MSB) first but the original specification has a LSBFE ("LSB-First Enable") to control whether data is transferred least (LSB) or most significant bit (MSB) first. On the clock edge, both master and slave shift out a bit to its counterpart. On the next clock edge, each receiver samples the transmitted bit and stores it in the shift register as the new least-significant bit. After all bits have been shifted out and in, the master and slave have exchanged register values. If more data needs to be exchanged, the shift registers are reloaded and the process repeats. Transmission may continue for any number of clock cycles. When complete, the master stops toggling the clock signal, and typically deselects the slave. If a single slave device is used, its pin may be fixed to logic low if the slave permits it. With multiple slave devices, a multidrop configuration requires an independent signal from the master for each slave device, while a daisy-chain configuration only requires one signal. Every slave on the bus that has not been selected should disregard the input clock and MOSI signals. And to prevent contention on MISO, non-selected slaves must use tristate output. Slaves that are not already tristate will need external tristate buffers to ensure this. and may also set up an interrupt routine when their slave select input line is pulled low or high. From slave to master SPI slaves sometimes use an out-of-band signal (another wire) to send an interrupt signal to a master. Examples include pen-down interrupts from touchscreen sensors, thermal limit alerts from temperature sensors, alarms issued by real-time clock chips, SDIO and audio jack insertions for an audio codec. Interrupts to master may also be faked by using polling (similarly to USB 1.1 and 2.0). == Bus topologies ==

Though the previous operation section focused on a basic interface with a single slave, SPI can instead communicate with multiple slaves using multidrop, daisy chain, or expander configurations. Multidrop configuration In the multidrop bus configuration, each slave has its own , and the master selects only one at a time. MISO, SCLK, and MOSI are each shared by all devices. This is the way SPI is normally used. Since the MISO pins of the slaves are connected together, they are required to be tri-state pins (high, low or high-impedance), where the high-impedance output must be applied when the slave is not selected. Slave devices not supporting tri-state may be used in multidrop configuration by adding a tri-state buffer chip controlled by its signal. (Since only a single signal line needs to be tristated per slave, one typical standard logic chip that contains four tristate buffers with independent gate inputs can be used to interface up to four slave devices to an SPI bus)Caveat: All signals should start high (to indicate no slaves are selected) before sending initialization messages to any slave, so other uninitialized slaves ignore messages not addressed to them. This is a concern if the master uses general-purpose input/output (GPIO) pins (which may default to an undefined state) for and if the master uses separate software libraries to initialize each device. One solution is to configure all GPIOs used for to output a high voltage for all slaves before running initialization code from any of those software libraries. Another solution is to add a pull-up resistor on each , to ensure that all signals are initially high. In addition to using SPI-specific slaves, daisy-chained SPI can include discrete shift registers for more pins of inputs (e.g. using the parallel-in serial-out 74xx165) or outputs (e.g. using the serial-in parallel-out 74xx595) chained indefinitely. Other applications that can potentially interoperate with daisy-chained SPI include SGPIO, JTAG, and I2C. Expander configurations Expander configurations use SPI-controlled addressing units (e.g. binary decoders, demultiplexers, or shift registers) to add chip selects. For example, one can be used for transmitting to a SPI-controlled demultiplexer an index number controlling its select signals, while another is routed through that demultiplexer according to that index to select the desired slave. ==Pros and cons==

Advantages • Full duplex communication in the default version of this protocol • Push-pull drivers (as opposed to open drain) provide relatively good signal integrity and high speed • Higher throughput than I²C or SMBus • SPI's protocol has no maximum clock speed, however: • Individual devices specify acceptable clock frequencies • Wiring and electronics limit frequency • Complete protocol flexibility for the bits transferred • Not limited to 8-bit symbols • Arbitrary choice of message size, content, and purpose • Simple hardware and interfacing • Hardware implementation for slaves only requires a selectable shift register • Slaves use the master's clock and hence do not need precision oscillators • Slaves do not need a unique address unlike I²C or GPIB or SCSI • Masters only additionally require generation of clock and signals • Results in simple bit-banged software implementation • Uses only four pins on IC packages, and wires in board layouts or connectors, much fewer than parallel interfaces • At most one unique signal per device (); all others are shared • The daisy-chain configuration does not need more than one shared • Typically lower power requirements than I²C or SMBus due to less circuitry (including pull up resistors) • Single master means no bus arbitration (and associated failure modes) - unlike CAN-bus • Transceivers are not needed - unlike CAN-bus • Signals are unidirectional, allowing for easy galvanic isolation Disadvantages • Requires more pins on IC packages than I²C, even in three-wire variants • Only handles short distances compared to RS-232, RS-485, or CAN-bus (though distance can be extended with the use of transceivers like RS-422) • Extensibility severely reduced when multiple slaves using different SPI Modes are required • Access is slowed down when master frequently needs to reinitialize in different modes • No formal standard • So validating conformance is not possible • Many existing variations complicate support • No built-in protocol support for some conveniences: • No hardware flow control by the slave (but the master can delay the next clock edge to slow the transfer rate) • No hardware slave acknowledgment (the master could be transmitting to nowhere and not know it) • No error-checking protocol • No hot swapping (dynamically adding nodes) • Interrupts are outside the scope of SPI (see ) ==Applications==

SPI is used to talk to a variety of peripherals, such as • Sensors: temperature, pressure, ADC, touchscreens, video game controllers • Control devices: audio codecs, digital potentiometers, DACs • Camera lenses: Canon EF lens mount • Memory: flash and EEPROMs • Any MMC or SD card (including SDIO variant) • Real-time clocks • LCDs, sometimes even for managing image data • Shift registers for additional I/O Chip or FPGA based designs sometimes use SPI to communicate between internal components; on-chip real estate can be as costly as its on-board cousin. And for high-performance systems, FPGAs sometimes use SPI to interface as a slave to a host, as a master to sensors, or for flash memory used to bootstrap if they are SRAM-based. The full-duplex capability makes SPI very simple and efficient for single master/single slave applications. Some devices use the full-duplex mode to implement an efficient, swift data stream for applications such as digital audio, digital signal processing, or telecommunications channels, but most off-the-shelf chips stick to half-duplex request/response protocols. ==Variations==

SPI implementations have a wide variety of protocol variations. Some devices are transmit-only; others are receive-only. Slave selects are sometimes active-high rather than active-low. Some devices send the least-significant bit first. Signal levels depend entirely on the chips involved. And while the baseline SPI protocol has no command codes, every device may define its own protocol of command codes. Some variations are minor or informal, while others have an official defining document and may be considered to be separate but related protocols. Original definition Motorola in 1983 listed three 6805 8-bit microcomputers that have an integrated "Serial Peripheral Interface", whose functionality is described in a 1984 manual. AN991 Motorola's 1987 Application Node AN991 "Using the Serial Peripheral Interface to Communicate Between Multiple Microcomputers" (now under NXP, last revised 2002) informally serves as the "official" defining document for SPI. Timing variations Some devices have timing variations from Motorola's CPOL/CPHA modes. Sending data from slave to master may use the opposite clock edge as master to slave. Devices often require extra clock idle time before the first clock or after the last one, or between a command and its response. Some devices have two clocks, one to read data, and another to transmit it into the device. Many of the read clocks run from the slave select line. Transmission size Different transmission word sizes are common. Many SPI chips only support messages that are multiples of 8 bits. Such chips can not interoperate with the JTAG or SGPIO protocols, or any other protocol that requires messages that are not multiples of 8 bits. No slave select Some devices do not use slave select, and instead manage protocol state machine entry/exit using other methods. Connectors Anyone needing an external connector for SPI defines their own or uses another standard connection such as: UEXT, Pmod, various JTAG connectors, Secure Digital card socket, etc. Flow control Some devices require an additional flow control signal from slave to master, indicating when data is ready. This leads to a 5-wire protocol instead of the usual 4. Such a ready or enable signal is often active-low, and needs to be enabled at key points such as after commands or between words. Without such a signal, data transfer rates may need to be slowed down significantly, or protocols may need to have dummy bytes inserted, to accommodate the worst case for the slave response time. Examples include initiating an ADC conversion, addressing the right page of flash memory, and processing enough of a command that device firmware can load the first word of the response. (Many SPI masters do not support that signal directly, and instead rely on fixed delays.) SafeSPI SafeSPI is an industry standard for SPI in automotive applications. Its main focus is the transmission of sensor data between different devices. High reliability modifications In electrically noisy environments, since SPI has few signals, it can be economical to reduce the effects of common mode noise by adapting SPI to use low-voltage differential signaling. Another advantage is that the controlled devices can be designed to loop-back to test signal integrity. Intelligent SPI controllers A Queued Serial Peripheral Interface (QSPI; different to but has same abbreviation as Quad SPI described in ) is a type of SPI controller that uses a data queue to transfer data across an SPI bus. It has a wrap-around mode allowing continuous transfers to and from the queue with only intermittent attention from the CPU. Consequently, the peripherals appear to the CPU as memory-mapped parallel devices. This feature is useful in applications such as control of an A/D converter. Other programmable features in Queued SPI are chip selects and transfer length/delay. SPI controllers from different vendors support different feature sets; such direct memory access (DMA) queues are not uncommon, although they may be associated with separate DMA engines rather than the SPI controller itself, such as used by Multichannel Buffered Serial Port (MCBSP). Most SPI master controllers integrate support for up to four slave selects, although some require slave selects to be managed separately through GPIO lines. Note that Queued SPI is different from Quad SPI, and some processors even confusingly allow a single "QSPI" interface to operate in either quad or queued mode! Three-wire Three-wire variants of SPI restricted to a half-duplex mode use a single bidirectional data line called SISO (slave out/slave in) or MOMI (master out/master in) instead of SPI's two unidirectional lines (MOSI and MISO). Three-wire tends to be used for lower-performance parts, such as small EEPROMs used only during system startup, certain sensors, and Microwire. Few SPI controllers support this mode, although it can be easily bit-banged in software. Bit-width extensions Dual SPI For instances where the full-duplex nature of SPI is not used, an extension uses both data pins in a half-duplex configuration to send two bits per clock cycle. Typically a command byte is sent requesting a response in dual mode, after which the MOSI line becomes SIO0 (serial I/O 0) and carries even bits, while the MISO line becomes SIO1 and carries odd bits. Data is still transmitted most-significant bit first, but SIO1 carries bits 7, 5, 3 and 1 of each byte, while SIO0 carries bits 6, 4, 2 and 0. This is particularly popular among SPI ROMs, which have to send a large amount of data, and comes in two variants: • Dual read sends the command and address from the master in single mode, and returns the data in dual mode. • Dual I/O sends the command in single mode, then sends the address and return data in dual mode. Quad SPI Quad SPI (QSPI; different to but has same abbreviation as Queued-SPI described in ) goes beyond dual SPI, adding two more I/O lines (SIO2 and SIO3) and sends 4 data bits per clock cycle. Again, it is requested by special commands, which enable quad mode after the command itself is sent in single mode. ; SQI Type 1: Commands sent on single line but addresses and data sent on four lines ; SQI Type 2: Commands and addresses sent on a single line but data sent/received on four lines QPI/SQI Further extending quad SPI, some devices support a "quad everything" mode where all communication takes place over 4 data lines, including commands. This is variously called "QPI" (not to be confused with Intel QuickPath Interconnect) or "serial quad I/O" (SQI) This requires programming a configuration bit in the device and requires care after reset to establish communication. Double data rate In addition to using multiple lines for I/O, some devices increase the transfer rate by using double data rate transmission. SGPIO SGPIO is essentially another (incompatible) application stack for SPI designed for particular backplane management activities. SGPIO uses 3-bit messages. Intel's Enhanced Serial Peripheral Interface Intel has developed a successor to its Low Pin Count (LPC) bus that it calls the Enhanced Serial Peripheral Interface (eSPI) bus. Intel aims to reduce the number of pins required on motherboards and increase throughput compared to LPC, reduce the working voltage to 1.8 volts to facilitate smaller chip manufacturing processes, allow eSPI peripherals to share SPI flash devices with the host (the LPC bus did not allow firmware hubs to be used by LPC peripherals), tunnel previous out-of-band pins through eSPI, and allow system designers to trade off cost and performance. An eSPI bus can either be shared with SPI devices to save pins or be separate from an SPI bus to allow more performance, especially when eSPI devices need to use SPI flash devices. The eSPI bus is also adopted by AMD Ryzen chipsets. == Interoperability with other standards ==

Microwire Microwire, often spelled μWire, is essentially a predecessor of SPI and a trademark of National Semiconductor. It's a strict subset of SPI: half-duplex, and using SPI mode 0. Microwire chips tend to need slower clock rates than newer SPI versions; perhaps 2 MHz vs. 20 MHz. Some Microwire chips also support a three-wire mode. Microwire/Plus Microwire/Plus is an enhancement of Microwire and features full-duplex communication and support for SPI modes 0 and 1. There was no specified improvement in serial clock speed. JTAG Although there are some similarities between SPI and the JTAG (IEEE 1149.1-2013) protocol, they are not interchangeable. JTAG is specifically intended to provide reliable test access to the I/O pins from an off-board controller with less precise signal delay and skew parameters, while SPI has many varied applications. While not strictly a level sensitive interface, the JTAG protocol supports the recovery of both setup and hold violations between JTAG devices by reducing the clock rate or changing the clock's duty cycles. Consequently, the JTAG interface is not intended to support extremely high data rates. ==Development tools==

Single-board computers Single-board computers may provide pin access to SPI hardware units. For instance, the Raspberry Pi's J8 header exposes at least two SPI units that can be used via Linux drivers or python. USB to SPI adapters There are a number of USB adapters that allow a desktop PC or smartphone with USB to communicate with SPI chips (e.g. CH341A/B based or FT221xs). They are used for embedded systems, chips (FPGA, ASIC, and SoC) and peripheral testing, programming and debugging. Many of them also provide scripting or programming capabilities (e.g. Visual Basic, C/C++, VHDL) and can be used with open source programs like flashrom, IMSProg, SNANDer or avrdude for flash, EEPROM, bootloader and BIOS programming. The key SPI parameters are: the maximum supported frequency for the serial interface, command-to-command latency, and the maximum length for SPI commands. It is possible to find SPI adapters on the market today that support up to 100 MHz serial interfaces, with virtually unlimited access length. SPI protocol being a de facto standard, some SPI host adapters also have the ability of supporting other protocols beyond the traditional 4-wire SPI (for example, support of quad-SPI protocol or other custom serial protocol that derive from SPI). Protocol analyzers Logic analyzers are tools which collect, timestamp, analyze, decode, store, and view the high-speed waveforms, to help debug and develop. Most logic analyzers have the capability to decode SPI bus signals into high-level protocol data with human-readable labels. Oscilloscopes SPI waveforms can be seen on analog channels (and/or via digital channels in mixed-signal oscilloscopes). Most oscilloscope vendors offer optional support for SPI protocol analysis (both 2-, 3-, and 4-wire SPI) with triggering. ==Alternative terminology==

Various alternative abbreviations for the four common SPI signals are used. (This section omits overbars indicating active-low.) • Serial clock • SCK, SCLK, CLK, SCL • Master Out Slave In (MOSI) • SIMO, MTSR, SPID - correspond to MOSI on both master and slave devices, connects to each other • SDI, DI, DIN, SI, SDA - on slave devices; various abbreviations for serial data in; connects to MOSI on master • SDO, DO, DOUT, SO - on master devices; various abbreviations for serial data out; connects to MOSI on slave • COPI, PICO for peripheral and controller, or COTI for controller and target • Master In Slave Out (MISO) • SOMI, MRST, SPIQ - correspond to MISO on both master and slave devices, connects to each other • SDO, DO, DOUT, SO - on slave devices; connects to MISO on master • SDI, DI, DIN, SI - on master devices; connects to MISO on slave • CIPO, POCI, ==See also==