Flynn's taxonomy

The four initial classifications defined by Flynn are based upon the number of concurrent instruction (or control) streams and data streams available in the architecture. Flynn defined three additional sub-categories of SIMD in 1972. SOLOMON predates Nvidia by more than 60 years. Pipelined processor which had just been announced at the time of writing of Flynn's paper. At the time that Flynn wrote his 1972 paper many systems were using main memory as the resource from which pipelines were reading and writing. When the resource that all "pipelines" read and write from is the scalar register file rather than main memory, modern variants of SIMD result. Examples include Altivec, NEON, and AVX. An alternative name for this type of register-based SIMD is "packed SIMD" and another is SIMD within a register (SWAR). Associative processor (Flynn's taxonomy: associative processing). The Linedancer, released in 2010, contained 4096 2-bit predicated SIMD ALUs, each with its own CAM, and was capable of 800 billion instructions per second. Aspex's ASP associative array SIMT processor predates NVIDIA by 20 years. There is some difficulty in classifying this processor according to Flynn's Taxonomy as it had both Associative Processing capability and Array processing, both under explicit programmer control. Multiple instruction streams, single data stream (MISD) Multiple instructions operate on one data stream. This is an uncommon architecture which is generally used for fault tolerance. Heterogeneous systems operate on the same data stream and must agree on the result. Examples include the Space Shuttle flight control computer. Multiple instruction streams, multiple data streams (MIMD) Multiple autonomous processors simultaneously execute different instructions on different data. MIMD architectures include multi-core superscalar processors, and distributed systems, using either one shared memory space or a distributed memory space. ==Diagram comparing classifications==

These four architectures are shown below visually. Each processing unit (PU) is shown for a uni-core or multi-core computer: File:SISD.svg File:MISD.svg File:SIMD.svg File:MIMD.svg ==Further divisions==

, all of the top 10 and most of the TOP500 supercomputers are based on a MIMD architecture. Although these are not part of Flynn's work, some further divide the MIMD category into the two categories below, and even further subdivisions are sometimes considered. Single program, multiple data streams (SPMD) Multiple autonomous processors simultaneously executing the same program (but at independent points, rather than in the lockstep that SIMD imposes) on different data. Also termed single process, multiple data The SPMD model and the term was proposed by Frederica Darema of the RP3 team. Multiple programs, multiple data streams (MPMD) Multiple autonomous processors simultaneously operating at least two independent programs. In HPC contexts, such systems often pick one node to be the "host" ("the explicit host/node programming model") or "manager" (the "Manager/Worker" strategy), which runs one program that farms out data to all the other nodes which all run a second program. Those other nodes then return their results directly to the manager. An example of this would be the Sony PlayStation 3 game console, with its SPU/PPU processor. MPMD is common in non-HPC contexts. For example, the make build system can build multiple dependencies in parallel, using target-dependent programs in addition to the make executable itself. MPMD also often takes the form of pipelines. A simple Unix shell command like ls | grep "A" | more launches three processes running separate programs in parallel with the output of one used as the input to the next. These are both distinct from the explicit parallel programming used in HPC in that the individual programs are generic building blocks rather than implementing part of a specific parallel algorithm. In the pipelining approach, the amount of available parallelism does not increase with the size of the data set. ==See also==