The chip measures 597.24 mm2 and consists of 2.75 billion
transistors fabricated in IBM's
32 nm CMOS silicon on insulator fabrication process, supporting speeds of 5.5
GHz, the highest clock speed CPU ever produced for commercial sale. The processor implements the
CISC z/Architecture with a
superscalar,
out-of-order pipeline and some new
instructions mainly related to
transactional execution. The cores have numerous other enhancements such as better
branch prediction, out of order execution and one dedicated co-processor for compression and cryptography. The instruction pipeline has 15 to 17 stages; the instruction queue can hold 40 instructions; and up to 90 instructions can be "in flight". It has six
cores, each with a private 64
KB L1 instruction cache, a private 96 KB L1 data cache, a private 1
MB L2 cache instruction cache, and a private 1 MB L2 data cache. In addition, there is a 48 MB shared L3 cache implemented in
eDRAM and controlled by two on-chip L3 cache controllers. There's also an additional shared L1 cache used for compression and cryptography operations. Each core has six
RISC-like execution units, including two
integer units, two
load–store units, one binary
floating-point unit and one
decimal floating point unit. The zEC12 chip can decode three instructions and execute seven operations in a single clock cycle. Attached to each core is a special co-processor accelerator unit; in the previous z CPU there were two shared by all four cores. The zEC12 chip has on board multi-channel
DDR3 RAM memory controller supporting a
RAID like configuration to recover from memory faults. The zEC12 also includes two
GX bus controllers for accessing host channel adapters and peripherals. ==Shared Cache==