Semiconductor device fabrication

Feature size (or process size) is determined by the width of the smallest lines that can be patterned in a semiconductor fabrication process; this measurement is known as the linewidth. Patterning often refers to photolithography which allows a device design or pattern to be defined on the device during fabrication. F2 is used as a measurement of area for different parts of a semiconductor device, based on the feature size of a semiconductor manufacturing process. Many semiconductor devices are designed in sections called cells, and each cell represents a small part of the device, such as a memory cell to store data. Thus F2 is used to measure the area taken up by these cells or sections. A specific semiconductor process has specific rules on the minimum size (width or CD/Critical Dimension) and spacing for features on each layer of the chip. Normally, a new semiconductor process has smaller minimum sizes and tighter spacing. In some cases, this allows a simple die shrink of a currently produced chip design to reduce costs, improve performance, and increase transistor density (number of transistors per unit area) without the expense of a new design. Early semiconductor processes had arbitrary names for generations (viz., HMOS I/II/III/IV and CHMOS III/III-E/IV/V). Later each new generation process became known as a technology node or process node, designated by the process' minimum feature size in nanometers (or historically micrometers) of the process's transistor gate length, such as the "90 nm process". However, this has not been the case since 1994, and the number of nanometers used to name process nodes (see the International Technology Roadmap for Semiconductors) has become more of a marketing term that has no standardized relation with functional feature sizes or with transistor density (number of transistors per unit area). Initially transistor gate length was smaller than that suggested by the process node name (e.g. 350 nm node); however, this trend reversed in 2009. ==History==

20th century In 1955, Carl Frosch and Lincoln Derick, working at Bell Telephone Laboratories, accidentally grew a layer of silicon dioxide over the silicon wafer, for which they observed surface passivation effects. By 1957 Frosch and Derick, using masking and predeposition, were able to manufacture silicon dioxide transistors; the first planar field effect transistors, in which drain and source were adjacent at the same surface. At Bell Labs, the importance of their discoveries was immediately realized. Memos describing the results of their work circulated at Bell Labs before being formally published in 1957. At Shockley Semiconductor, Shockley had circulated the preprint of their article in December 1956 to all his senior staff, including Jean Hoerni, who would later invent the planar process in 1959 while at Fairchild Semiconductor. In 1948, Bardeen patented an insulated-gate transistor (IGFET) with an inversion layer; Bardeen's concept forms the basis of MOSFET technology today. An improved type of MOSFET technology, CMOS, was developed by Chih-Tang Sah and Frank Wanlass at Fairchild Semiconductor in 1963. CMOS was commercialised by RCA in the late 1960s. Many early semiconductor device manufacturers developed and built their own equipment such as ion implanters. In 1963, Harold M. Manasevit was the first to document epitaxial growth of silicon on sapphire while working at the Autonetics division of North American Aviation (now Boeing). In 1964, he published his findings with colleague William Simpson in the Journal of Applied Physics. In 1965, C.W. Mueller and P.H. Robinson fabricated a MOSFET (metal–oxide–semiconductor field-effect transistor) using the silicon-on-sapphire process at RCA Laboratories. Semiconductor device manufacturing has since spread from Texas and California in the 1960s to the rest of the world, including Asia, Europe, and the Middle East. Wafer size has grown over time, from 25 mm (1 inch) in 1960, to 50 mm (2 inches) in 1969, 100 mm (4 inches) in 1976, 125 mm (5 inches) in 1981, 150 mm (6 inches) in 1983 and 200 mm in 1992. In the era of 2-inch wafers, these were handled manually using tweezers and held manually for the time required for a given process. Tweezers were replaced by vacuum wands as they generate fewer particles which can contaminate the wafers. Wafer carriers or cassettes, which can hold several wafers at once, were developed to carry several wafers between process steps. However, since wafers still had to be individually removed, processed, and returned, acid-resistant carriers were later introduced so the entire cassette could be dipped directly into wet etching and cleaning tanks, eliminating this time-consuming process. When wafer sizes increased to 100 mm, the entire cassette would often not be dipped as uniformly, and the quality of the results across the wafer became hard to control. By the time 150 mm wafers arrived, the cassettes were not dipped and were only used as wafer carriers and holders to store wafers, and robotics became prevalent for handling wafers. With 200 mm wafers, manual handling of wafer cassettes becomes risky as they are heavier. In the 1970s and 1980s, several companies migrated their semiconductor manufacturing technology from bipolar to MOSFET technology. Semiconductor manufacturing equipment has been considered costly since 1978. In 1984, KLA developed the first automatic reticle and photomask inspection tool. In 1985, KLA developed an automatic inspection tool for silicon wafers, which replaced manual microscope inspection. In 1985, SGS (now STmicroelectronics) invented BCD, also called BCDMOS, a semiconductor manufacturing process using bipolar, CMOS and DMOS devices. Applied Materials developed the first practical multi-chamber, or cluster wafer processing tool, the Precision 5000. Until the 1980s, physical vapor deposition was the primary technique used for depositing materials onto wafers, until the advent of chemical vapor deposition. Equipment with diffusion pumps was replaced with those using turbomolecular pumps, as the latter do not use oil, which often contaminates wafers during processing in vacuum. 200 mm diameter wafers were first used in 1990 and became the standard until the introduction of 300 mm diameter wafers in 2000. Bridge tools were used in the transition from 150 mm wafers to 200 mm wafers and in the transition from 200 mm to 300 mm wafers. The semiconductor industry has adopted larger wafers to cope with the increased demand for chips as larger wafers provide more surface area per wafer. Over time, the industry shifted to 300 mm wafers which brought along the adoption of FOUPs, but many products that are not advanced are still produced in 200 mm wafers such as analog ICs, RF chips, power ICs, BCDMOS and MEMS devices. Some processes such as cleaning, ion implantation, etching, annealing and oxidation started to adopt single wafer processing instead of batch wafer processing to improve the reproducibility of results. A similar trend existed in MEMS manufacturing. In 1998, Applied Materials introduced the Producer, a cluster tool that had chambers grouped in pairs for processing wafers, which shared common vacuum and supply lines but were otherwise isolated, which was revolutionary at the time as it offered higher productivity than other cluster tools without sacrificing quality, due to the isolated chamber design. They also have facilities spread in different countries. As the average utilization of semiconductor devices increased, durability became an issue and manufacturers started to design their devices to ensure they last for enough time, and this depends on the market the device is designed for. This especially became a problem at the 10 nm node. Silicon on insulator (SOI) technology has been used in AMD's 130 nm, 90 nm, 65 nm, 45 nm and 32 nm single, dual, quad, six and eight core processors made since 2001. During the transition from 200 mm to 300 mm wafers in 2001, many bridge tools were used which could process both 200 mm and 300 mm wafers. At the time, 18 companies could manufacture chips in the leading edge 130 nm process. In 2006, 450 mm wafers were expected to be adopted in 2012, and 675 mm wafers were expected to be used by 2021. Since 2009, "node" has become a commercial name for marketing purposes that indicates new generations of process technologies, without any relation to gate length, metal pitch or gate pitch. For example, GlobalFoundries' 7 nm process was similar to Intel's 10 nm process, thus the conventional notion of a process node has become blurred. Additionally, TSMC and Samsung's 10 nm processes are only slightly denser than Intel's 14 nm in transistor density. They are actually much closer to Intel's 14 nm process than they are to Intel's 10 nm process (e.g. Samsung's 10 nm processes' fin pitch is the same as that of Intel's 14 nm process: 42 nm). Intel has changed the name of its 10 nm process to position it as a 7 nm process. As transistors become smaller, new effects start to influence design decisions, such as self-heating of the transistors, and other effects, such as electromigration, have become more evident since the 16nm node. In 2011, Intel demonstrated Fin field-effect transistors (FinFETs), where the gate surrounds the channel on three sides, allowing for increased energy efficiency and lower gate delay—and thus greater performance—over planar transistors at the 22 nm node, because planar transistors which only have one surface acting as a channel, started to suffer from short channel effects. A startup called SuVolta created a technology called Deeply Depleted Channel (DDC) to compete with FinFET transistors; it uses very lightly doped planar transistors at the 65 nm node. By 2018, a number of transistor architectures had been proposed for the eventual replacement of FinFET, most of which were based on the concept of GAAFET: horizontal and vertical nanowires, horizontal nanosheet transistors (Samsung MBCFET, Intel Nanoribbon), vertical FET (VFET) and other vertical transistors, complementary FET (CFET), stacked FET, vertical TFETs, FinFETs with III-V semiconductor materials (III-V FinFET), several kinds of horizontal gate-all-around transistors such as nano-ring, hexagonal wire, square wire, and round wire gate-all-around transistors and negative-capacitance FET (NC-FET) which uses drastically different materials. FD-SOI was seen as a potential low cost alternative to FinFETs. As of 2019, 14 nm process and 10 nm process chips are in mass production by Intel, UMC, TSMC, Samsung, Micron, SK Hynix, Toshiba Memory and GlobalFoundries, with 7 nm process chips in mass production by TSMC and Samsung, although their 7 nm node definition is similar to Intel's 10 nm process. The 5 nm process began being produced by Samsung in 2018. As of 2019, the node with the highest transistor density is TSMC's 5nm N5 node, with a density of 171.3million transistors per square millimeter. In 2019, Samsung and TSMC announced plans to produce 3 nm process nodes. GlobalFoundries has decided to stop the development of new nodes beyond 12 nm to save resources, as it has determined that setting up a new fab to handle sub-12 nm orders would be beyond the company's financial abilities. From 2020 to 2023, there was a global chip shortage. During this shortage caused by the COVID-19 pandemic, many semiconductor manufacturers banned employees from leaving company grounds. Many countries granted subsidies to semiconductor companies for building new fabrication plants or fabs. Many companies were affected by counterfeit chips. Semiconductors have become vital to the world economy and the national security of some countries. The US has asked TSMC to not produce semiconductors for Huawei, a Chinese company. CFET transistors were explored, which stacks NMOS and PMOS transistors on top of each other. Two approaches were evaluated for constructing these transistors: a monolithic approach which built both types of transistors in one process, and a sequential approach which built the two types of transistors separately and then stacked them. ==List of steps==

This is a list of processing techniques that are employed numerous times throughout the construction of a modern electronic device; this list does not necessarily imply a specific order, nor that all techniques are taken during manufacture as, in practice the order and which techniques are applied, are often specific to process offerings by foundries, or specific to an integrated device manufacturer (IDM) for their own products, and a semiconductor device might not need all techniques. Equipment for carrying out these processes is made by a handful of companies. All equipment needs to be tested before a semiconductor fabrication plant is started. These processes are done after integrated circuit design. A semiconductor fab operates 24/7 and many fabs use large amounts of water, primarily for rinsing the chips. • Wafer processing (also called front end) • Wet cleans • Cleaning by solvents such as acetone, trichloroethylene or ultrapure water sometimes while spinning the wafer • Piranha solution • RCA clean • Wafer scrubbing • Spin cleaning • Jet spray cleaning • Megasonics • Immersion batch cleaning • Surface passivation • Photolithography • Photoresist coating (often as a liquid, on the entire wafer) • Photoresist baking (solidification in an oven) • Edge bead removal • Exposure (in a photolithography stepper, scanner or mask aligner) • Post-Exposure Baking (PEB) improves the durability of the photoresist • Development (removal of parts of the resist by application of a liquid developer, leaving only parts of the wafer exposed for ion implantation, layer deposition, etching, etc) • Hardmask creation • Ion implantation (in which dopants are embedded in the wafer, creating regions of increased or decreased conductivity) • Etching (microfabrication) • Dry etching (plasma etching) • Reactive-ion etching (RIE) • Deep reactive-ion etching (DRIE) • Atomic layer etching (ALE) • Plasma ALE • Thermal ALE • Molecular beam epitaxy (MBE) • Ion beam deposition • Plasma ashing (for complete photoresist removal/photoresist stripping, also known as dry strip, historically done with a chemical solvent called a resist stripper, to allow wafers to undergo another round of photolithography) • Thermal treatments • Rapid thermal processing (RTP), rapid thermal anneal • Millisecond thermal processing, millisecond anneal, millisecond processing, flash lamp anneal (FLA) • Laser anneal • Furnace anneals • Thermal oxidation • LOCOS • Laser lift-off (for LED production) • Electrochemical deposition (ECD). See Electroplating. • Chemical-mechanical polishing (CMP) • Wafer testing (where the electrical performance is verified using automatic test equipment, binning and/or laser trimming may also be carried out at this step) • Die preparation • Through-silicon via manufacture (for three-dimensional integrated circuits) • Wafer mounting (wafer is mounted onto a metal frame using dicing tape) • Wafer backgrinding and polishing (reduces the thickness of the wafer for thin devices like a smartcard or PCMCIA card or wafer bonding and stacking, this can also occur during wafer dicing, in a process known as Dice Before Grind or DBG) • Wafer bonding and stacking (for three-dimensional integrated circuits and MEMS) • Redistribution layer manufacture (for WLCSP packages) • Wafer bumping (for flip chip BGA (ball grid array), and WLCSP packages) • Die cutting or wafer dicing • IC packaging • Die attachment (The die is attached to a leadframe using conductive paste or die attach film.) • IC bonding: Wire bonding, thermosonic bonding, flip chip or tape automated bonding (TAB) • IC encapsulation or integrated heat spreader (IHS) installation • Molding (using special plastic molding compound that may contain glass powder as filler to control thermal expansion) • Baking • Electroplating (plates the copper leads of the lead frames with tin to make soldering easier) • Laser marking or silkscreen printing • Trim and form (separates the lead frames from each other, and bends the lead frame's pins so that they can be mounted on a printed circuit board) • IC testing Additionally, steps such as Wright etch may be carried out. ==Prevention of contamination and defects==

When feature widths were far greater than about 10 micrometres, semiconductor purity was not as big of an issue as it is today in device manufacturing. In the 1960s, workers could work on semiconductor devices in street clothing. As devices become more integrated, cleanrooms must become even cleaner. Today, fabrication plants are pressurized with filtered air to remove even the smallest particles, which could come to rest on the wafers and contribute to defects. The ceilings of semiconductor cleanrooms have fan filter units (FFUs) at regular intervals to constantly replace and filter the air in the cleanroom; semiconductor capital equipment may also have its own FFUs to clean air in the equipment's EFEM, which allows the equipment to receive wafers in FOUPs. The FFUs, combined with raised floors with grills, help ensure a laminar air flow, to ensure that particles are immediately brought down to the floor and do not stay suspended in the air due to turbulence. The workers in a semiconductor fabrication facility are required to wear cleanroom suits to protect the devices from contamination by humans. ==Wafers==

A typical wafer is made out of extremely pure silicon that is grown into mono-crystalline cylindrical ingots (boules) up to 300 mm (slightly less than 12 inches) in diameter using the Czochralski process. These ingots are then sliced into wafers about 0.75 mm thick and polished to obtain a very regular and flat surface. During the production process wafers are often grouped into lots, which are represented by a FOUP, SMIF or a wafer cassette, which are wafer carriers. FOUPs and SMIFs can be transported in the fab between machines and equipment with an automated OHT (Overhead Hoist Transport) AMHS (Automated Material Handling System). ==Processing==

In semiconductor device fabrication, the various processing steps fall into four general categories: deposition, removal, patterning, and modification of electrical properties. • Deposition is any process that grows, coats, or otherwise transfers a material onto the wafer. Available technologies include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD) among others. Deposition can be understood to include oxide layer formation, by thermal oxidation or, more specifically, LOCOS. • Removal is any process that removes material from the wafer; examples include etch processes (either wet or dry) and chemical-mechanical planarization (CMP). • Patterning is the shaping or altering of deposited materials, and is generally referred to as lithography. For example, in conventional lithography, the wafer is coated with a chemical called a photoresist; then, a machine called an aligner or stepper focuses a mask image on the wafer using short-wavelength light; the exposed regions (for "positive" resist) are washed away by a developer solution. The wafer then undergoes etching where materials not protected by the mask are removed. After removal or other processing, the remaining photoresist is removed by "dry" stripping/plasma ashing/resist ashing or by "wet" resist stripper chemistry. Wet etching was widely used in the 1960s and 1970s, but it was replaced by dry etching/plasma etching starting at the 10 micron to 3 micron nodes. This is because wet etching makes undercuts (etching under mask layers or resist layers with patterns). Dry etching has become the dominant etching technique. • Modification of electrical properties has historically entailed doping transistor sources and drains and polysilicon. Doping consists of introducing impurities into the atomic structure of a semiconductor material in order to modify its electrical properties. Initially thermal diffusion with furnaces at 900 to 1200 °C with gases containing dopants were used for doping wafers and there was resistance against ion implantation as it still required a separate furnace but ion implantation ultimately prevailed in the 1970s as it offers better reproducibility of results during manufacturing of chips, Ion implantation is practical because of the high sensitivity of semiconductor devices to foreign atoms, as ion implantation does not deposit large numbers of atoms. Process variability is a challenge in semiconductor processing, in which wafers are not processed evenly or the quality or effectiveness of processes carried out on a wafer are not even across the wafer surface. Front-end-of-line (FEOL) processing Wafer processing is separated into FEOL and BEOL stages. FEOL processing refers to the formation of the transistors directly in the silicon. The raw wafer is engineered by the growth of an ultrapure, virtually defect-free silicon layer through epitaxy. In the most advanced logic devices, prior to the silicon epitaxy step, tricks are performed to improve the performance of the transistors to be built. One method involves introducing a straining step wherein a silicon variant such as silicon-germanium (SiGe) is deposited. Once the epitaxial silicon is deposited, the crystal lattice becomes stretched somewhat, resulting in improved electronic mobility. Another method, called silicon on insulator technology, involves the insertion of an insulating layer between the raw silicon wafer and the thin layer of subsequent silicon epitaxy. This method results in the creation of transistors with reduced parasitic effects. Semiconductor equipment may have several chambers that process wafers in processes such as deposition and etching. Many pieces of equipment handle wafers between these chambers in an internal nitrogen or vacuum environment to improve process control. At the 90nm node, transistor channels made with strain engineering were introduced to improve drive current in PMOS transistors by introducing regions with Silicon-Germanium in the transistor. The same was done in NMOS transistors at the 20nm node. technology in the 1970s. High-k dielectric such as hafnium oxide (HfO2) replaced silicon oxynitride (SiON), to prevent large amounts of leakage current in the transistor while allowing for continued scaling or shrinking of the transistors. However, HfO2 is not compatible with polysilicon gates; it requires the use of a metal gate. Two approaches were used in production: gate-first and gate-last. Gate-first consists of depositing the high-k dielectric and then the gate metal such as Tantalum nitride whose workfunction depends on whether the transistor is NMOS or PMOS, polysilicon deposition, gate line patterning, source and drain ion implantation, dopant anneal, and silicidation of the polysilicon and the source and drain. In DRAM memories this technology was first adopted in 2015. Gate-last consisted of first depositing the High-κ dielectric, creating dummy gates, manufacturing sources and drains by ion deposition and dopant annealing, depositing an "interlevel dielectric (ILD)" and then polishing, and removing the dummy gates to replace them with a metal whose workfunction depended on whether the transistor was NMOS or PMOS, thus creating the metal gate. A third process, full silicidation (FUSI) was not pursued due to manufacturing problems. Gate-first became dominant at the 22nm/20nm node. HKMG has been extended from planar transistors for use in FinFET and nanosheet transistors. Hafnium silicon oxynitride can also be used instead of Hafnium oxide. Since the 16 nm/14 nm node, Atomic layer etching (ALE) is increasingly used for etching as it offers higher precision than other etching methods. In production, plasma ALE is commonly used, which removes materials unidirectionally, creating structures with vertical walls. Thermal ALE can also be used to remove materials isotropically, in all directions at the same time but without the capability to create vertical walls. Plasma ALE was initially adopted for etching contacts in transistors, and since the 7nm node it is also used to create transistor structures by etching them. was state-of-the-art. Since the 22nm node, some manufacturers have added a new process called middle-of-line (MOL) which connects the transistors to the rest of the interconnect made in the BEoL process. The MOL is often based on tungsten and has upper and lower layers: the lower layer connects the junctions of the transistors, and an upper layer which is a tungsten plug that connects the transistors to the interconnect. Intel at the 10nm node introduced contact-over-active-gate (COAG) which, instead of placing the contact for connecting the transistor close to the gate of the transistor, places it directly over the gate of the transistor to improve transistor density. Interconnect through four layers of planarized copper interconnect, down to the polysilicon (pink), wells (greyish) and substrate (green) Historically, the metal wires have been composed of aluminum. In this approach to wiring (often called subtractive aluminum), blanket films of aluminum are deposited first, patterned, and then etched, leaving isolated wires. Dielectric material is then deposited over the exposed wires. The various metal layers are interconnected by etching holes (called "vias") in the insulating material and then depositing tungsten in them with a CVD technique using tungsten hexafluoride; this approach can still be (and often is) used in the fabrication of many memory chips such as dynamic random-access memory (DRAM), because the number of interconnect levels can be small (no more than four). The aluminum was sometimes alloyed with copper for preventing recrystallization. Gold was also used in interconnects in early chips. More recently, as the number of interconnect levels for logic has substantially increased due to the large number of transistors that are now interconnected in a modern microprocessor, the timing delay in the wiring has become so significant as to prompt a change in wiring material (from aluminum to copper interconnect layer) alongside a change in dielectric material in the interconnect (from silicon dioxides to newer low-κ insulators). This performance enhancement also comes at a reduced cost via damascene processing, which eliminates processing steps. As the number of interconnect levels increases, planarization of the previous layers is required to ensure a flat surface prior to subsequent lithography. Without it, the levels would become increasingly crooked, extending outside the depth of focus of available lithography, and thus interfering with the ability to pattern. CMP (chemical-mechanical planarization) is the primary processing method to achieve such planarization, although dry etch back is still sometimes employed when the number of interconnect levels is no more than three. Copper interconnects use an electrically conductive barrier layer to prevent the copper from diffusing into ("poisoning") its surroundings, often made of tantalum nitride. In 2014, Applied Materials proposed the use of cobalt in interconnects at the 22nm node, used for encapsulating copper interconnects in cobalt to prevent electromigration, replacing tantalum nitride since it needs to be thicker than cobalt in this application. ==Wafer metrology==

The highly serialized nature of wafer processing has increased the demand for metrology in between the various processing steps. For example, thin film metrology based on ellipsometry or reflectometry is used to tightly control the thickness of gate oxide, as well as the thickness, refractive index, and extinction coefficient of photoresist and other coatings. Wafer metrology equipment/tools, or wafer inspection tools are used to verify that the wafers haven't been damaged by previous processing steps up until testing; if too many dies on one wafer have failed, the entire wafer is scrapped to avoid the costs of further processing. Virtual metrology has been used to predict wafer properties based on statistical methods without performing the physical measurement itself. ==Device test==

Once the front-end process has been completed, the semiconductor devices or chips are subjected to a variety of electrical tests to determine if they function properly. The percent of devices on the wafer found to perform properly is referred to as the yield. Manufacturers are typically secretive about their yields, but it can be as low as 30%, meaning that only 30% of the chips on the wafer work as intended. Process variation is one among many reasons for low yield. Testing is carried out to prevent faulty chips from being assembled into relatively expensive packages. The yield is often but not necessarily related to device (die or chip) size. As an example, in December 2019, TSMC announced an average yield of ~80%, with a peak yield per wafer of >90% for their 5nm test chips with a die size of 17.92 mm2. The yield went down to 32% with an increase in die size to 100 mm2. The number of killer defects on a wafer, regardless of die size, can be noted as the defect density (or D0) of the wafer per unit area, usually cm2. The fab tests the chips on the wafer with an electronic tester that presses tiny probes against the chip. The machine marks each bad chip with a drop of dye. Currently, electronic dye marking is possible if wafer test data (results) are logged into a central computer database and chips are "binned" (i.e. sorted into virtual bins) according to predetermined test limits such as maximum operating frequencies/clocks, number of working (fully functional) cores per chip, etc. The resulting binning data can be graphed, or logged, on a wafer map to trace manufacturing defects and mark bad chips. This map can also be used during wafer assembly and packaging. Binning allows chips that would otherwise be rejected to be reused in lower-tier products, as is the case with GPUs and CPUs, increasing device yield, especially since very few chips are fully functional (have all cores functioning correctly, for example). eFUSEs may be used to disconnect parts of chips such as cores, either because they did not work as intended during binning, or as part of market segmentation (using the same chip for low, mid and high-end tiers). Chips may have spare parts to allow the chip to fully pass testing even if it has several non-working parts. Chips are also tested again after packaging, as the bond wires may be missing, or analog performance may be altered by the package. This is referred to as the "final test". Chips may also be imaged using x-rays. Usually, the fab charges for testing time, with prices on the order of cents per second. Testing times vary from a few milliseconds to a couple of seconds, and the test software is optimized for reduced testing time. Multiple chip (multi-site) testing is also possible because many testers have the resources to perform most or all of the tests in parallel and on several chips at once. Chips are often designed with "testability features" such as scan chains or a "built-in self-test" to speed testing and reduce testing costs. In certain designs that use specialized analog fab processes, wafers are also laser-trimmed during testing, in order to achieve tightly distributed resistance values as specified by the design. Good designs try to test and statistically manage corners (extremes of silicon behavior caused by a high operating temperature combined with the extremes of fab processing steps). Most designs cope with at least 64 corners. ==Device yield==

Device yield or die yield is the number of working chips or dies on a wafer, given in percentage since the number of chips on a wafer (Die per wafer, DPW) can vary depending on the chips' size and the wafer's diameter. Yield degradation is a reduction in yield, which historically was mainly caused by dust particles, however since the 1990s, yield degradation is mainly caused by process variation, the process itself and by the tools used in chip manufacturing, although dust still remains a problem in many older fabs. Dust particles have an increasing effect on yield as feature sizes are shrunk with newer processes. Automation and the use of mini environments inside of production equipment, FOUPs and SMIFs have enabled a reduction in defects caused by dust particles. Device yield must be kept high to reduce the selling price of the working chips since working chips have to pay for those chips that failed, and to reduce the cost of wafer processing. Yield can also be affected by the design and operation of the fab. Tight control over contaminants and the production process are necessary to increase yield. Contaminants may be chemical contaminants or be dust particles. "Killer defects" are those caused by dust particles that cause complete failure of the device (such as a transistor). There are also harmless defects. A particle needs to be 1/5 the size of a feature to cause a killer defect. So if a feature is 100 nm across, a particle only needs to be 20 nm across to cause a killer defect. Electrostatic electricity can also affect yield adversely. Chemical contaminants or impurities include heavy metals such as iron, copper, nickel, zinc, chromium, gold, mercury and silver, alkali metals such as sodium, potassium and lithium, and elements such as aluminum, magnesium, calcium, chlorine, sulfur, carbon, and fluorine. It is important for these elements to not remain in contact with the silicon, as they could reduce yield. Chemical mixtures may be used to remove these elements from the silicon; different mixtures are effective against different elements. Several models are used to estimate yield. They are Murphy's model, Poisson's model, the binomial model, Moore's model and Seeds' model. There is no universal model; a model has to be chosen based on actual yield distribution (the location of defective chips). For example, Murphy's model assumes that yield loss occurs more at the edges of the wafer (non-working chips are concentrated on the edges of the wafer), Poisson's model assumes that defective dies are spread relatively evenly across the wafer, and Seeds's model assumes that defective dies are clustered together. Smaller dies cost less to produce (since more fit on a wafer, and wafers are processed and priced as a whole), and can help achieve higher yields since smaller dies have a lower chance of having a defect, due to their lower surface area on the wafer. However, smaller dies require smaller features to achieve the same functions of larger dies or surpass them, and smaller features require reduced process variation and increased purity (reduced contamination) to maintain high yields. Metrology tools are used to inspect the wafers during the production process and predict yield, so wafers predicted to have too many defects may be scrapped to save on processing costs. ==Die preparation==

Once tested, a wafer is typically reduced in thickness in a process also known as "backlap", before the wafer is scored and then broken into individual dies, a process known as wafer dicing. Only the good, unmarked chips are packaged. ==Packaging==

After the dies are tested for functionality and binned, they are packaged. Plastic or ceramic packaging involves mounting the die, connecting the die/bond pads to the pins on the package, and sealing the die. Tiny bondwires are used to connect the pads to the pins. In the 'old days' (1970s), wires were attached by hand, but now specialized machines perform the task. Traditionally, these wires have been composed of gold, leading to a lead frame (pronounced "leed frame") of solder-plated copper; lead is poisonous, so lead-free "lead frames" are now mandated by RoHS. Traditionally the bond pads are located on the edges of the die, however, Flip-chip packaging can be used to place bond pads across the entire surface of the die. Chip scale package (CSP) is another packaging technology. A plastic dual in-line package, like most packages, is many times larger than the actual die hidden inside, whereas CSP chips are nearly the size of the die; a CSP can be constructed for each die before the wafer is diced. The packaged chips are retested to ensure that they were not damaged during packaging and that the die-to-pin interconnect operation was performed correctly. A laser then etches the chip's name and numbers on the package. The steps involving testing and packaging of dies, followed by final testing of finished, packaged chips, are called the back end, ATMP (Assembly, Test, Marking, and Packaging) or ATP (Assembly, Test and Packaging) of semiconductor manufacturing, and may be carried out by OSAT (OutSourced Assembly and Test) companies which are separate from semiconductor foundries. A foundry is a company or fab performing manufacturing processes such as photolithography and etching that are part of the front end of semiconductor manufacturing. ==Hazardous materials==

Many toxic materials are used in the fabrication process. These include: • poisonous elemental dopants, such as arsenic, antimony, and phosphorus. • poisonous compounds, such as arsine and phosphine containing arsenic and phosphorus respectively, used in ion implantation doping, tungsten hexafluoride, used in CVD deposition of tungsten in transistor interconnects, silane used for depositing polysilicon, Trichlorosilane used to create high purity polysilicon which is used for silicon photovoltaics or for polysilicon for the Czochralski process used to make monocrystalline silicon wafers, or for depositing silicon films • highly reactive liquids, such as hydrogen peroxide, fuming nitric acid, sulfuric acid, and hydrofluoric acid, used in etching and cleaning. It is vital that workers not be directly exposed to these dangerous substances. The high degree of automation common in the IC fabrication industry helps to reduce the risks of exposure. Most fabrication facilities employ exhaust management systems, such as wet scrubbers, combustors, heated absorber cartridges, etc., to control the risk to workers and to the environment. ==See also==