80960MC The i960MC included all of the features of the original BiiN system; but these were simply not mentioned in the specifications, leading some to wonder why the i960MC was so large and had so many pins - 53 out of 132 - labeled "no connect". Later iterations of the i960, like the 80960Jx series, have a more typical number of "do no connect" and use more power and ground pins and have additional I/O pins instead. However, these "no connect" pins are actually not connected internally and unrelated to the BiiN feature set - the silicon die inside does not have bond pads for them. The 80960MC contains an on-chip
memory management unit and supports
fault tolerant systems in conjunction with Intel's M82965 Bus Extension Unit as well. Both chips meet the
MIL-STD-883C standard. Both chips became available in the first quarter of 1989 with the price of US$2400 and US$1700 respectively. Extended temperature samples became available in August 1988 as well. It contains 32 32-bit registers, a 512 byte instruction cache, a
stack frame cache, a high speed 32-bit
multiplexed burst bus, and an interrupt controller. It also has 256 interrupt vectors and 32 levels of interrupt priority. to have been the first single-chip
superscalar RISC implementation. The C-series included only one ALU, but could dispatch and execute an arithmetic instruction, a memory reference, and a branch instruction at the same time, and sustain two instructions per cycle under certain circumstances. The first versions released ran at 33 MHz, and Intel promoted the chip as capable of 66 MIPS. The i960CA microarchitecture was designed in 1987–1988 and formally announced on September 12, 1989. Later, in May 1992, came the i960CF, which included a larger instruction cache (4 KB instead of 1 KB) and added 1 KB of data cache, but was still without an FPU or MMU.
80960MX The 80960MX is a superscalar implementation of the Extended architecture, executing up to three instructions per clock execution for sustained performance of 25 VAX MIPS. It implemented the Joint Industrial Avionics Working Group (JIAWG) 32-bit ISA standard. It was originally packaged in a 348 lead ceramic pin grid array and later supplied as a bare die. The i960 MX supports object-oriented programming. A 33rd tag bit distinguished between a 32-bit data word and a 32-bit pointer to memory. This prohibited forged pointers to protected areas of memory.
80960Jx The 80960Jx is a processor for embedded applications. It features a 32-bit multiplexed address/data bus, instruction and data cache, 1K on-chip RAM, interrupt controller, and two independent 32-bit timers. The 80960Jx's testability features included ONCE (on-circuit emulation) mode and boundary scan (
JTAG).
80960HA, 80960HD, 80960HT The 80960Hx processors offered upgraded performance from the Cx variants by offering clock multiplication, larger 16K instruction cache and 4k data cache, and a GMU (Guarded Memory Unit). The HD variant had an internal 2× clock multiplication while the HT version has a 3x clock multiplication, allowing increased performance without external bus speed changes.
80960VH Announced in October 1998, the i960VH Embedded-PCI processor featured a 32-bit 33 MHz
PCI bus and 100 MHz i960JT processor core. The core also featured 16 KB of instruction cache, 4 KB of data cache, and 1 KB of built-in RAM. Other core features included two 32-bit timers, programmable interrupt controller,
I²C interface, and a two-channel DMA controller.
80960Rx The 80960Rx processors were labeled as I/O Processors and included an implementation of the
PCI Bus (2.1 or 2.2 depending on the variant) as well as a 80960Jx core. These could be used on motherboards to implement on-board PCI device as well as on PCI expansion cards. The RM/RN/RS variants used a JT core with a 3x bus to core multiplication to achieve 100 MHz internal clock speeds, while the RD variant used a JF core with 2× multiplication to achieve 66 MHz. The RP variant had a JF core that ran at the 33 MHz bus speed. ==Variant specifications==