The input current is offset by a
negative feedback current flowing in the capacitor, which is generated by an increase in output voltage of the amplifier. The output voltage is therefore dependent on the value of input current it has to offset and the inverse of the value of the feedback capacitor. The greater the capacitor value, the less output voltage has to be generated to produce a particular feedback current flow. The input capacitance of the circuit is almost zero because of the
Miller effect. This ensures that the stray capacitances (the cable capacitance, the amplifier input capacitance, etc.) are virtually grounded and have no influence on the output signal.
Ideal circuit This circuit operates by passing a current that charges or discharges the
capacitor C_\text{F} during the time under consideration, which strives to retain the
virtual ground condition at the input by off-setting the effect of the input current: Referring to the above diagram, if the op-amp is assumed to be
ideal, then the voltage at the inverting (-) input is held equal to the voltage at the non-inverting (+) input as a
virtual ground. The input voltage passes a current V_\text{in}/{R_1} through the
resistor producing a compensating current flow through the series capacitor to maintain the virtual ground. This charges or discharges the capacitor over time. Because the resistor and capacitor are connected to a virtual ground, the input current does not vary with capacitor charge, so a
linear integration that works across all frequencies is achieved (unlike ). The circuit can be analyzed by applying
Kirchhoff's current law at the inverting input: :i_{\text{1}} = I_{\text{B}} + i_{\text{F}} For an ideal op-amp, I_{\text{B}} = 0 amps, so: :i_{\text{1}} = i_{\text{F}} Furthermore, the capacitor has a voltage-current relationship governed by the equation: :i_{\text{F}} = C_\text{F} \frac{d(V_\text{2} - V_\text{o})}{dt} Substituting the appropriate variables: :\frac{V_{\text{in}} - V_{\text{2}}}{R_{\text{1}}} = C_{\text{F}}\frac{d(V_{\text{2}} - V_{\text{o}})}{dt} For an ideal op-amp, V_2 = 0 volts, so: :\frac{V_{\text{in}}}{R_{\text{1}}} = -C_{\text{F}}\frac{dV_{\text{o}}}{dt} Integrating both sides with respect to time: : \int_0^t\frac{V_{\text{in}}}{R_{\text{1}}} \ dt\ = - \int_0^t C_{\text{F}} \frac{dV_{\text{o}}}{dt} \, dt If the initial value of V_\text{o} is assumed to be 0 volts, the output voltage will simply be proportional to the integral of the input voltage: :V_{\text{o}} = -\frac{1}{R_{\text{1}}C_{\text{F}}}\int_0^t V_{\text{in}}\, dt
Practical circuit This practical integrator attempts to address a number of flaws of the ideal integrator circuit: Real op-amps have a finite
open-loop gain, an
input offset voltage (V_\text{OS}) and input bias currents (I_\text{B}), which may not be well-matched and may be distinguished as I_\text{B-} going into the inverting input and I_\text{B+} going into the non-inverting input. This can cause several issues for the ideal design; most importantly, if V_{\text{in}} = 0, both the output offset voltage and the input bias current I_\text{B-} can cause current to pass through the capacitor, causing the output voltage to drift over time until the op-amp saturates. Similarly, if V_{\text{in}} were a signal centered about zero volts (i.e. without a
DC component), no drift would be expected in an ideal circuit, but may occur in a real circuit. To negate the effect of the input bias current, it is necessary for the non-inverting terminal to include a resistor R_{\text{om}}=R_1 || R_\text{F} || R_\text{L} , which simplifies to R_1 provided that R_1 is much smaller than the load resistance R_L and the feedback resistance R_F. Well-matched input bias currents then cause the same voltage drop of R_1 I_\text{B} at both the inverting and non-inverting terminals, to effectively cancel out the effect of bias current at those inputs. A
CMOS op amp should be selected to minimize errors from input bias current, Also, in a DC steady state, an ideal capacitor acts as an open circuit. The DC gain of the ideal circuit is therefore infinite (or in practice, the open-loop gain of a non-ideal op-amp). Any DC (or very low frequency) component may then cause the op amp output to drift into saturation. To prevent this, the DC gain can be limited to a finite value by inserting a large resistor R_\text{F} in parallel with the
feedback capacitor. Note that some op amps have a large internal feedback resistor, and many real capacitors have
leakage that is effectively a large feedback resistor. The addition of these resistors turns the output drift into a finite, preferably small, DC error voltage: :V_\text{error} = \left( \frac{R_\text{F}}{R_1} + 1 \right) \left( V_\text{OS} + I_\text{B-} \left( R_\text{F} \parallel R_1 \right) \right) . There are other methods, which may be combined, to deal with offset error. A variation of this circuit simply uses an adjustable voltage source instead of R_{\text{om}} and some op amps with very low offset voltage may not even require offset correction. Offset correction is a bigger concern for older op amps, particularly BJT types. Another variation circuit to avoid offset correction that works for AC signals only is to capacitively-couple the input with a large input capacitor before R_1 which will naturally charge up to the offset voltage. Additionally, because offset may drift over time and temperature, some op amps provide null offset pins, which can be connected to a potentiometer whose wiper connects to the negative supply to allow readjusting when conditions change. It should also be noted that the integrator is commonly used as part of a feedback/
servo loop which provides the DC feedback path, removing the need for a feedback resistor. ==Frequency response==