Larrabee can be considered a hybrid between a
multi-core CPU and a
GPU, and has similarities to both. Its
coherent cache hierarchy and
x86 architecture compatibility are CPU-like, while its wide
SIMD vector units and texture sampling hardware are GPU-like. As a GPU, Larrabee would have supported traditional rasterized
3D graphics (
Direct3D &
OpenGL) for games. However, its hybridization of CPU and GPU features should also have been suitable for
general purpose GPU (GPGPU) or
stream processing tasks. For example, it might have performed
ray tracing or
physics processing, in
real time for games or offline for scientific research as a component of a
supercomputer. Larrabee's early presentation drew some criticism from GPU competitors. At
NVISION 08, an
Nvidia employee called Intel's
SIGGRAPH paper about Larrabee "marketing puff" and quoted an industry analyst (
Peter Glaskowsky) who speculated that the Larrabee architecture was "like a
GPU from 2006". By June 2009, Intel claimed that prototypes of Larrabee were on par with the
Nvidia GeForce GTX 285.
Justin Rattner, Intel
CTO, delivered a keynote at the Supercomputing 2009 conference on November 17, 2009. During his talk he demonstrated an overclocked Larrabee processor topping one teraFLOPS in performance. He claimed this was the first public demonstration of a single-chip system exceeding one teraFLOPS. He pointed out this was early silicon, thereby leaving open the question on eventual performance for the architecture. Because this was only one fifth that of available competing graphics boards, Larrabee was cancelled "as a standalone discrete graphics product" on December 4, 2009. The P54C-derived core is
superscalar but does not include
out-of-order execution, though it has been updated with modern features such as
x86-64 support, • It included one major
fixed-function graphics hardware feature:
texture sampling units. These perform
trilinear and
anisotropic filtering and
texture decompression. • It included explicit cache control instructions to reduce
cache thrashing during streaming operations which only read/write data once. but Intel never announced any plans for this. Though Larrabee's native C/C++ compiler included auto-vectorization and many applications were able to execute correctly after having been recompiled, maximum efficiency was expected to have required code optimization using C++ vector intrinsics or inline Larrabee assembly code.
Comparison with the Cell broadband engine Larrabee's philosophy of using many small, simple cores was similar to the ideas behind the
Cell processor. There are some further commonalities, such as the use of a high-bandwidth ring bus to communicate between cores. The team working on Larrabee was separate from the Intel GMA team. The hardware was designed by a newly formed team at Intel's
Hillsboro, Oregon, site, separate from those that designed the
Nehalem. The software and drivers were written by a newly formed team. The 3D stack specifically was written by developers at
RAD Game Tools (including
Michael Abrash). The Intel Visual Computing Institute researched basic and applied technologies that could be applied to Larrabee-based products. ==Projected performance data==