Panther Lake combines a heterogeneous CPU core tile manufactured on Intel's in-house
18A process with an integrated graphics tile based on the Arc Xe3 architecture, which is derived from the earlier Xe2 (Battlemage) design, and an I/O tile manufactured on TSMC's N6 process. The clusters vary in size: The big 4+8+4 core tile is used in the H series, and the small 4+4 core tile is used in the low-power processors. Non-Arc H series CPUs also are the only processors in this lineup to utilize the larger I/O tile, while Arc H series and low-power CPUs use the smaller core tile. Said tiles both support DDR5 and LPDDR5X memory, however, the larger tile has more PCIe lanes. Arc H series CPUs use a binned version of the smaller I/O tile that doesn't support DDR5. There are also smaller GPU tiles which have up to 4 Xe cores, and larger GPU tiles which have up to 12 Xe tiles. The latter being branded and labeled as Arc B390/B370 If the machine using it reaches memory speeds of at least LPDDR5X-7467, otherwise they will be labeled as just Intel Graphics. Some models with the larger GPU tile continue to rely on
TSMC manufacturing for the GPU on its N3E process, possibly due to budget concerns. Rather than introducing a fundamentally new CPU or GPU architecture, Panther Lake focuses on higher core counts, better graphics configurations, and increased power budgets enabled by a newer manufacturing node and modular tile-based design Furthermore, instead of developing a more capable NPU, Intel has opted for an optimized, smaller and more efficient NPU that delivers about the same performance as the previous generation's NPU. == Reception ==