In terms of its instruction set architecture, MicroBlaze is similar to the
RISC-based
DLX architecture described in a popular computer architecture book by
Patterson and
Hennessy. With few exceptions, the MicroBlaze can issue a new instruction every cycle, maintaining single-cycle throughput under most circumstances. The MicroBlaze has a versatile interconnect system to support a variety of embedded applications. MicroBlaze's primary I/O bus, the
AXI interconnect, is a system-memory mapped transaction bus with master–slave capability. Older versions of the MicroBlaze used the
CoreConnect PLB bus. The majority of vendor-supplied and third-party IP interface to AXI directly (or through an AXI interconnect). For access to local-memory (FPGA
RAM), MicroBlaze uses a dedicated LMB bus, which provides fast on-chip storage. User-defined coprocessors are supported through dedicated AXI4-Stream connections. The coprocessor(s) interface can accelerate computationally intensive algorithms by offloading parts or the entirety of the computation to a user-designed hardware module. Many aspects of the MicroBlaze can be user configured: cache size, pipeline depth (3-stage, 5-stage, or 8-stage), embedded peripherals,
memory management unit, and bus-interfaces can be customized. The area-optimized version of MicroBlaze, which uses a 3-stage pipeline, sacrifices clock frequency for reduced logic area. The performance-optimized version expands the execution pipeline to 5 stages, allowing top speeds of more than 700
MHz (on Virtex UltraScale+
FPGA family). Also, key
processor instructions which are rarely used but more expensive to implement in hardware can be selectively added/removed (e.g. multiply, divide, and floating point operations). This customization enables a developer to make the appropriate design trade-offs for a specific set of host hardware and application software requirements. With the memory management unit, MicroBlaze is capable of hosting operating systems requiring hardware-based paging and protection, such as the
Linux kernel. Otherwise it is limited to operating systems with a simplified protection and virtual memory model, e.g.
FreeRTOS or
Linux without MMU support. MicroBlaze's overall throughput is substantially less than a comparable hard CPU core (such as the
ARM Cortex-A9 in the
Zynq). MicroBlaze V is based on the
RISC-V architecture.
Fast Simplex Link Fast Simplex Link (FSL) is a 32-bit wide interface on
MicroBlaze. The FSL channels are uni-directional, point-to-point
data streaming interfaces. A MicroBlaze processor supports up to eight FSL channels. This interface allows MicroBlaze processors to communicate with peripherals or other processors. The FSL can be used for extending the processor execution unit with custom
hardware accelerators thanks to a low latency dedicated
interface to the processor pipeline. In addition, the same FSL channel can be used to transmit or receive either control or data words. The interface is
FIFO, and a separate bit indicates whether the transmitted, or received, word is control or data information. FSL has low latency compared to
CoreConnect's On-chip Peripheral Bus. ==Vivado==