Multi-channel memory architecture

Multi-channel memory requires a capable memory controller (which may be on the motherboard/chipset or integrated into the CPU). The memory modules installed into matching banks, each of which belongs to a different channel. The motherboard's manual will provide an explanation of how to install memory for that particular unit. For dual-channel use, the matched pair of memory modules may usually be placed in the first bank of each channel, and a different-capacity pair of modules in the second bank. Extent of matching Modules rated at different speeds can be run in multi-channel mode, although the motherboard will then run all memory modules at the speed of the slowest module. Some motherboards, however, have compatibility issues with certain brands or models of memory when attempting to use them in multi-channel mode. For this reason, it is generally advised to use identical pairs of memory modules, which is why most memory manufacturers now sell "kits" of matched-pair DIMMs. Several motherboard manufacturers only support configurations where matched modules are used. A matching pair needs to match in: • Capacity (e.g. 1024 MB). • Speed (e.g. PC5300). • Memory timing, including (Column Address Strobe) latency or CL and other parameters. • Number of memory ranks and the bus width of each chip. This is often written in forms such as 2Rx4 (two ranks containing four-bit chips). • The rank count is not always the same as the number of sides (there can be more than two), but single-sided DIMMs generally only have one rank. • The number of ranks and their widths would also determine how many chips there are, so visual inspection can often spot obvious incompatibilities. Of these requirements, only the clock and timing are absolutely required to match as the channels work in lockstep by definition. (If speed is not the same, the lower speed of the two modules will be used. Likewise, the higher latency of the two modules will be used.) The size and rank count requirements have loosened over time, starting with Intel's introduction of Flex Memory in 2004, which allows two modules of different size to work in a combination of dual and single channel, and AMD's introduction of an equivalent feature some time before 2015. Mixing of bus widths remains flaky, especially for ECC setups. Some systems such as Broadwell-EP do not support Flex Memory, but do allow capacity in the form of "summing". For example, a channel containing 1 DIMM (stick) of 2Rx4 16GB can be matched with a channel containing 2 DIMMs of 1Rx4 8GB. The total rank count as well as capacity ends up matched per channel. Although Flex Memory is an official feature (and some success has been reported with larger channel counts), mixing of module types is generally not documented as supported for triple-channel and above. This is especially true of server hardware. Theoretically any matched set of modules may be used in either single- or multi-channel operation, provided the motherboard supports the choice of channel count. == Dual-channel architecture ==

Dual-channel-enabled memory controllers in a PC system architecture use two 64-bit data channels. Dual-channel should not be confused with double data rate (DDR), in which data exchange happens twice per DRAM clock. The two technologies are independent of each other, and many motherboards use both by using DDR memory in a dual-channel configuration. Performance Theoretically, dual-channel configurations double the memory bandwidth and reduce the memory latency when compared to single-channel configurations. This should not be confused with double data rate (DDR) memory, which doubles the usage of DRAM bus by transferring data both on the rising and falling edges of the memory bus clock signals. Ganged versus unganged Dual-channel was originally conceived as a way to maximize memory throughput by combining two 64-bit buses into a single 128-bit bus. This is retrospectively called the "ganged" mode. However, due to lackluster performance gains in consumer applications, more modern implementations of dual-channel use the "unganged" mode by default, which maintains two 64-bit memory buses but allows independent access to each channel, in support of multithreading with multi-core processors. "Ganged" versus "unganged" difference could also be envisioned as an analogy with the way RAID 0 works, when compared to JBOD. With RAID 0 (which is analogous to "ganged" mode), it is up to the additional logic layer to provide better (ideally even) usage of all available hardware units (storage devices, or memory modules) and increased overall performance. On the other hand, with JBOD (which is analogous to "unganged" mode) it is relied on the statistical usage patterns to ensure increased overall performance through even usage of all available hardware units. Also, on LPDDR DRAMs, each memory controller is 32 bits wide. As of LPDDR5, each memory chip can connect to a memory controller using 1 16-bit sub-channel or 2 16-bit sub-channels, allowing each memory controller to serve one or two chips. == Triple-channel architecture ==

Operation DDR3 triple-channel architecture is used in the Intel Core i7-900 series (the Intel Core i7-800 series only support up to dual-channel). The LGA 1366 platform (e.g. Intel X58) supports DDR3 triple-channel, normally 1333 and 1600Mhz, but can run at higher clock speeds on certain motherboards. AMD Socket AM3 processors do not use the DDR3 triple-channel architecture but instead use dual-channel DDR3 memory. The same applies to the Intel Core i3, Core i5 and Core i7-800 series, which are used on the LGA 1156 platforms (e.g., Intel P55). According to Intel, a Core i7 with DDR3 operating at 1066 MHz will offer peak data transfer rates of 25.6 GB/s when operating in triple-channel interleaved mode. This, Intel claims, leads to faster system performance as well as higher performance per watt. When operating in triple-channel mode, memory latency is reduced due to interleaving, meaning that each module is accessed sequentially for smaller bits of data rather than completely filling up one module before accessing the next one. Data is spread amongst the modules in an alternating pattern, potentially tripling available memory bandwidth for the same amount of data, as opposed to storing it all on one module. On Intel platforms as new as the LGA 2011, triple-channel can only be used when all three, or a multiple of three, memory modules are identical in capacity and speed, and are placed in three-channel slots. When two memory modules are installed, the architecture will operate in dual-channel architecture mode. Supporting processors Intel Core i7: • Intel Core i7-9xx Bloomfield, Gulftown • Intel Core i7-9x0X Gulftown Intel Xeon: • Intel Xeon E55xx Nehalem-EP • Intel Xeon E56xx Westmere-EP • Intel Xeon ECxxxx Jasper Forest • Intel Xeon L55xx Nehalem-EP • Intel Xeon L5609 Westmere-EP • Intel Xeon L5630 Westmere-EP • Intel Xeon L5640 Westmere-EP • Intel Xeon LC55x8 Jasper Forest • Intel Xeon Wxxxx Bloomfield, Nehalem-EP, Westmere-EP • Intel Xeon X55xx Nehalem-EP • Intel Xeon X56xx Westmere-EP • Intel Xeon x4xx v3 • Intel Pentium 14xx v3 • Intel Xeon x4xx v2 • Intel Pentium 14xx v2 • Intel Xeon x4xx • Intel Pentium 14xx == Quad-channel architecture ==

Operation Quad-channel memory debuted on Intel's Nehalem-EX LGA 1567 platform of Xeon CPUs, aka Beckton in 2010, and was introduced to the high end product line on the Intel X79 LGA 2011 platform with Sandy Bridge-E in late 2011. DDR4 replaced DDR3 on the Intel X99 LGA 2011 platform, aka Haswell-E, and is also used in AMD's Threadripper platform. DDR3 quad-channel architecture is used in the AMD G34 platform and in the aforementioned Intel CPUs prior to Haswell. AMD processors for the C32 platform and Intel processors for the LGA 1155 platform (e.g. Intel Z68) use dual-channel DDR3 memory instead. On Intel platforms as new as the LGA 2011, the quad-channel architecture can be used only when all four memory modules (or a multiple of four) are identical in capacity and speed, and are placed in quad-channel slots. When two memory modules are installed, the architecture will operate in a dual-channel mode; When three memory modules are installed, the architecture will operate in a triple-channel mode. Other tests performed by TweakTown on the same subject showed no significant differences in performance, leading to a conclusion that not all benchmark software is up to the task of exploiting increased parallelism offered by the multi-channel memory configurations. • Opteron 6200-series "Interlagos" (32 nm) • Opteron 6100-series "Magny-Cours" (45 nm) Intel Core: • Intel Core i9-10900X • Intel Core i7-9800X • Intel Core i9-7980XE • Intel Core i9-7940X • Intel Core i9-7900X • Intel Core i7-7820X • Intel Core i7-7800X • Intel Core i7-6950X • Intel Core i7-6900K • Intel Core i7-6850K • Intel Core i7-6800K • Intel Core i7-5960X • Intel Core i7-5930K • Intel Core i7-5820K • Intel Core i7-4960X • Intel Core i7-4930K • Intel Core i7-4820K • Intel Core i7-3970X • Intel Core i7-3960X • Intel Core i7-3930K • Intel Core i7-3820 Intel Xeon: • Intel Xeon E5-x6xx v4 • Intel Xeon E7-x8xx v3 • Intel Xeon E5-x6xx v3 • Intel Xeon E7-x8xx v2 • Intel Xeon E5-x6xx v2 • Intel Xeon E7-x8xx • Intel Xeon E5-x6xx == Hexa-channel architecture ==

Supported by Qualcomm Centriq server processors, and processors from the Intel Xeon Scalable platform. == Octa-channel architecture ==

Supported by Cavium ThunderX2 server processors, AMD's server processors from their Epyc platform, and the Threadripper PRO lineup of professional-class workstation processors. == Dodeca-channel architecture ==

Dodeca-channel or 12-channel memory architecture is introduced with AMD's server processors from their Epyc 9004 platform released in 2022, using DDR5 memory. == Other types of memory ==

The NAND flash memory can include flash channel and flash sub-channel, which accessed by the flash memory controller. The number of flash channel increases, the delay of raw flash memory (such as ONFI based NAND flash) decreases, and the bandwidth of raw flash memory increases. A typical NAND flash chip can include 1, 2 or 4 sub-channels. == See also ==