Goldmont Plus is an enhanced 2nd generation
out-of-order low-power
Atom microarchitecture designed for entry level desktop and notebook computers. Goldmont Plus is built on the 14 nm manufacturing process and supports up to four cores for the consumer devices. It includes the
Intel Gen9 graphics architecture with improvements introduced with the
Kaby Lake microarchitecture. The Goldmont Plus microarchitecture builds on the success of the Goldmont microarchitecture, and provides the following enhancements: • Widened previous generation Atom processor back-end
pipeline to 4-wide allocation to 4-wide retire, while maintaining 3-wide fetch and decode pipeline. • Enhanced
branch prediction unit. • 64 KB shared second level pre-decode cache (16 KB in Goldmont microarchitecture). • Larger
reservation station and
re-order buffer entries to support large out-of-order window. • Wider integer
execution unit. New dedicated JEU port with support for faster branch redirection. •
Radix-1024
floating point divider for fast scalar/packed single, double and extended precision floating point divides. • Improved
AES-NI instruction latency and throughput. • Larger
load and store buffers. Improved store-to-load forwarding latency store data from register. • Shared instruction and data second level
TLB.
Paging cache enhancements (PxE/ePxE caches). • Modular system design with four cores sharing up to 4 MB
L2 cache. • Support for Read Processor ID (RDPID) new instruction. == Technology ==