The package on a package technique tries to combine the benefits of traditional packaging with the benefits of
die-stacking techniques, while avoiding their drawbacks. Traditional packaging places each die in its own package, a package designed for normal PCB assembly techniques that place each package directly on the PCB side-by-side. The
3D die-stacking system in package (SiP) techniques stacks multiple die in a single package, which has several advantages and also some disadvantages compared to traditional PCB assembly. In embedded PoP techniques, chips are embedded in a substrate on the bottom of the package. This PoP technology enables smaller packages with shorter electrical connections and is supported by companies such as
Advanced Semiconductor Engineering (ASE).
Advantages over traditional isolated-chip packaging The most obvious benefit is motherboard space savings. PoP uses much less PCB area, almost as little as stacked-die packages. Electrically, PoP offers benefits by minimizing track length between different interoperating parts, such as a controller and memory. This yields better electrical performance of devices, since shorter routing of interconnections between circuits yields faster signal propagation and reduced noise and cross-talk.
Advantages over chip stacking There are several key differences between stacked-die and stacked-package products. The main financial benefit of package on a package is that the memory device is decoupled from the logic device. Therefore this gives PoP all the same advantages that traditional packaging has over stacked-die products: • The memory package can be tested separately from the logic package • Only "known good" packages are used in final assembly (if the memory is bad only the memory is discarded and so on). Compare this to stacked-die packages where the entire set is useless and rejected if either the memory or logic is bad. • The end user (such as makers of
mobile phones or
digital cameras) controls the logistics. This means memory from different suppliers can be used at different times without changing the logic. The memory becomes a commodity to be sourced from the lowest cost supplier. This trait is also a benefit compared to PiP (package in package) which requires a specific memory device to be designed in and sourced upstream of the end user. • Any mechanically mating top package can be used. For a low-end phone, a smaller memory configuration may be used on the top package. For a high-end phone, more memory could be used with the same bottom package. This simplifies inventory control by the OEM. For a stacked-die package or even PiP (package in package), the exact memory configuration must be known weeks or months in advance. • Because the memory only comes into the mix at final assembly, there is no reason for logic suppliers to source any memory. With a stacked-die device, the logic provider must buy wafers of memory from a memory supplier. ==JEDEC standardization==