The three initial Radeon Instinct products were announced on December 12, 2016, and released on June 20, 2017, with each based on a different architecture.
MI6 The MI6 is a passively cooled,
Polaris 10 based card with 16 GB of
GDDR5 memory and with a <150
W TDP.
MI8 The MI8 is a
Fiji based card, analogous to the R9 Nano, has a <175W TDP.
MI25 The MI25 is a
Vega based card, utilizing HBM2 memory. The MI25 performance is expected to be 12.3 TFLOPS using FP32 numbers. In contrast to the MI6 and MI8, the MI25 is able to increase performance when using lower precision numbers, and accordingly is expected to reach 24.6 TFLOPS when using FP16 numbers. The MI25 is rated at <300W TDP with passive cooling. The MI25 also provides 768 GFLOPS peak double precision (FP64) at 1/16th rate.
MI50, MI60 MI50 and MI60 are based on the Vega20 variant of GCN 5. They support 1/2 rate FP64 and are the last Instinct cards to bear the Radeon branding as well as the ability to produce display output.
MI100 series (CDNA 1) The CDNA1 cards have removed all rendering-related resources while adding matrix processing units.
MI300 series The MI300A and MI300X are data center accelerators that use the
CDNA 3 architecture, which is optimized for high-performance computing (HPC) and generative artificial intelligence (AI) workloads. The CDNA 3 architecture features a scalable chiplet design that leverages TSMC’s advanced packaging technologies, such as CoWoS (chip-on-wafer-on-substrate) and InFO (integrated fan-out), to combine multiple chiplets on a single interposer. The chiplets are interconnected by AMD’s Infinity Fabric, which enables high-speed and low-latency data transfer between the chiplets and the host system. The MI300A is an accelerated processing unit (APU) that integrates 24
Zen 4 CPU cores with four CDNA 3 GPU cores, resulting in a total of 228 CUs in the GPU section, and 128 GB of HBM3 memory. The Zen 4 CPU cores are based on the 5 nm process node and support the x86-64 instruction set, as well as AVX-512 and BFloat16 extensions. The Zen 4 CPU cores can run general-purpose applications and provide host-side computation for the GPU cores. The MI300A has a peak performance of 61.3 TFLOPS of FP64 (122.6 TFLOPS FP64 matrix) and 980.6 TFLOPS of FP16 (1961.2 TFLOPS with sparsity), as well as 5.3 TB/s of memory bandwidth. The MI300A supports PCIe 5.0 and CXL 2.0 interfaces, which allow it to communicate with other devices and accelerators in a heterogeneous system. The MI300X is a dedicated generative AI accelerator that replaces the CPU cores with additional GPU cores and HBM memory, resulting in a total of 304 CUs (64 cores per CU) and 192 GB of HBM3 memory. The MI300X is designed to accelerate generative AI applications, such as natural language processing, computer vision, and deep learning. The MI300X has a peak performance of 653.7 TFLOPS of TP32 (1307.4 TFLOPS with sparsity) and 1307.4 TFLOPS of FP16 (2614.9 TFLOPS with sparsity), as well as 5.3 TB/s of memory bandwidth. The MI300X also supports PCIe 5.0 and CXL 2.0 interfaces, as well as AMD’s ROCm software stack, which provides a unified programming model and tools for developing and deploying generative AI applications on AMD hardware.
MI350 series The MI350X and MI355X are data center accelerators built on the CDNA 4 architecture, targeting advanced AI training and inference workloads. Manufactured on TSMC’s 3 nm (N3) process, they incorporate a high-performance chiplet design, feature 288 GB of HBM3E memory with 8 TB/s of bandwidth. CDNA 4 introduces native support for low-precision formats FP4 and FP6, in addition to FP8 and FP16—boosting FP4 compute to up to 9.2 PetaFLOPS on the MI355X. The architecture maintains AMD’s Infinity Fabric interconnect for high-speed, low-latency data transit between GPU chiplets and the host system. This design builds on CDNA 3, advancing both scalability and energy efficiency for large-scale AI deployments. == Software ==