MIL-STD-1750A

The 1750A supports 216 16-bit words of memory for the core standard. The standard defines an optional memory management unit that allows 220 16-bit words of memory using 512 page mapping registers (in the I/O space), defining separate instruction and data spaces, and keyed memory access control. Most instructions are 16 bits, although some have a 16-bit extension. The standard computer has 16 general purpose 16-bit registers (0 through 15). Registers 1 through 15 can be used as index registers. Registers 12 through 15 can be used as base registers. Any of the 16 registers can be used as a stack pointer for the SJS and URS instructions (stack jump subroutine and unstack return subroutine), but only register 15 is used as the stack pointer for the PSHM and POPM instructions (push multiple and pop multiple). The computer has instructions for 16- and 32-bit binary arithmetic, as well as 32- and 48-bit floating point. I/O is generally via the I/O instructions (XIO and VIO), which have a separate 216 16-bit word address space and may have a specialized bus. == Implementations ==

Because MIL-STD-1750A does not define implementation details, 1750A products are available from a wide variety of companies in the form of component, board, and system-level offerings implemented in myriad technologies, often the most advanced and exotic of their respective periods (e.g. GaAs, ECL, SoS). 1750A systems often offer high levels of protection from radiation and other hazardous environments, making them particularly suited for military, aviation and space applications. Examples of MIL-STD-1750A implementations include: • CPU Technology, Inc. CPU1750A-FB, a high performance 1750A SOC designed to give existing applications a late life performance boost. • Delco Systems Operations Magic V 1750 Processor • Dynex Semiconductor MAS281. A radiation hardened SOC implementation on a 64-pin multichip module with an optional MMU. • GEC-Plessey RH1750, a radiation-hardened version for aerospace and space flight applications. GEC-Plessey, under its previous iteration as Marconi Electronic Devices, also initially developed the MAS281 and MA31750A series of processors, later made available through Dynex Semiconductor • Honeywell HX1750, fabricated on Honeywell's Silicon on Insulator CMOS (SOI-IV) process giving radiation hardness. The HX1750 includes an FPU and peripherals on chip. • IBM Federal Systems AP-102, a member of the System/4 Pi Advanced Processor series (used in various roles including the USAF F-111 avionics upgrade) • Johns Hopkins University Applied Physics Laboratory (JHU/APL) MIL-STD-1750AAV space flight qualified processor. A multi-board silicon on sapphire implementation specifically designed for space flight. • Marconi Electronic Devices MIL-STD-1750A. • McDonnell-Douglas MD-281. A radiation hardened SoS three-die implementation on a 64-pin multichip module. • Fairchild Semiconductor F9450 series. • National Semiconductor PACE P1750A. The PACE normally runs a version of the Data General Nova instruction set, but was adapted to run MIL-STD-1750A using new microcode. The family includes the P1750A CPU, the P1750AE Enhanced CPU, the P1753 Memory Management Unit (MMU), the P1754 Processor Interface Chip (PIC) and the P1757ME Multi-Chip Module. This line was passed to Performance Semiconductor and then Pyramid Semiconductor in 2003. • Royal Aircraft Establishment Farnborough MIL-STD-1750A implementation in AMD 2901 bit-slice technology. == Programming ==

Processors based on MIL-STD-1750A are often programmed in JOVIAL, a high-level programming language defined by the United States Department of Defense which is derived from ALGOL 58. Later, Ada was heavily used. There are also C compilers, for example Cleanscape XTC-1750A. Older versions of GNU GCC contain support for MIL-STD-1750A; it was declared obsolete in version 3.1, and removed in subsequent versions. In addition, DDC-I provides its SCORE Integrated Development Environment (IDE) with both Ada95 and C compilers, and TADS (Tartan Ada Development System) Ada83 development environment, both targeting processors based on MIL-STD-1750A. == Deployments ==

The U.S. Air Force defined the standard in order to have a common computing architecture and thereby reduce the costs of software and computer systems for all military computing needs. This includes embedded tasks such as aircraft and missile control systems as well as more mundane general military computing needs. The advantages of this concept are recognized outside of the USAF, and the 1750A has been adopted by other organizations such as the European Space Agency, NASA, Israeli Aircraft Industries, and many projects in academia. Examples of military aircraft using the 1750A include: • IAI Lavi fighter • US Army AH-64D Apache Longbow Helicopter • USAF F-16 Digital Flight Control System and Fire Control Computer • USN F-18 RFCS Flight Control Computer Use in space Fully space-rated implementations make the 1750A one of the few types of computers that are applicable for use in deep space applications. Example spacecraft that use the 1750A are: • EOS Aqua, Aura and Terra • ESA Cluster • ESA Envisat - Envisat's ASAR instrument, built by Matra Marconi Space and comprising the Central Electronics Sub-Assembly and Antenna Sub-Assembly used a total of 42 GEC-Plessey MA31750A processors in a dual-redundant configuration • ESA Rosetta • ESA Mars Express • ESA Venus Express • EUMETSAT Metop • ISRO GSAT/INSAT/IRS series of spacecraft • ISRO Mars Orbiter Mission • ISRO Space Recovery Experiment-1 Guidance and Navigation Computer • Midcourse Space Experiment (MSX) spacecraft developed at JHU/APL • MSTI-1, 2 and 3 • NASA Cassini • NASA Landsat 7 • NASA Mars Global Surveyor • Naval Research Laboratory Clementine Lunar Orbiter • NOAA GOES-13, GOES-O and GOES-P • Orbital Sciences Corporation commercial communication satellite platforms • USAF Titan-4 Guidance Computer == 1750B ==

The MIL-STD-1750B was to be a successor architecture to the MIL-STD-1750A, with added and expanded features, some of which were optional. By the mid-1980s there was a published draft of the 1750B available, and some vendors began implementations for it. However, no finalized specification was ever issued for the 1750B, as military and industry attention shifted to 32-bit architectural alternatives such as the MIPS R3000. == References ==