===
Burroughs large system architectures=== Burroughs introduced segmentation on the
B5000, followed by the compatible B5500 and B5700. The later
B6500 replaced the Program Reference Table (PRT) with a
Saguaro stack, changed control word formats, changed
descriptor formats and changed the mechanism for referring to a control word or descriptor.
B5000, B5500 and B5700 Words in the
B5000, B5500 and B5700 are 48 bits long.
Descriptors have the uppermost bit set in the word. They reside in either the Program Reference Table (PRT) or the stack, and contain a
presence bit indicating whether the data are present in memory. There are distinct data and program descriptors. The tag bits indicate the type of data contained in the word; there are several descriptor types, indicated by different tag bit values. (DAT) and 24-bit addresses,
control register 0 specifies a segment size of either 64 KiB or 1 MiB and a page size of either 2 KiB or 4 KiB; control register 1 contains a Segment Table Designator (STD), which specifies the length and real address of the segment table. Each segment table entry contains a page table location, a page table length and an invalid bit. IBM later expanded the address size to 31 bits and added two bits to the segment table entries: ;Segment-protection bit :Segment is read-only ;Common-segment bit :The segment is shared between address spaces; this bit is set to optimize TLB use Each of IBM's DAT implementations includes a translation cache, which IBM called a Translation Lookaside Buffer (TLB). While Principles of Operation discusses the TLB in general terms, the details are not part of the architecture and vary from model to model. Starting with the
3031, 3032, and 3033 processor complexes, IBM offered a feature called
Dual-address Space (DAS), which allows a program to switch between the translation tables for two address spaces, referred to as
primary address space (CR1) and
secondary address space (CR7), and to move data between the address spaces subject to protection key. DAS supports a translation table to convert a 16-bit address space number (ASN) to an STD, with privileged instructions to load the STD into CR1 (primary) or CR7 (secondary).
x86 architecture Early
x86 processors, beginning with the
Intel 8086, provide crude memory segmentation and no
memory protection (every byte of each segment is always available to any program.) The 16-bit segment registers allow for 65,536 segments; each segment begins at a fixed offset equal to 16 times the segment number; the segment starting address granularity is 16 bytes. Each segment grants read-write access to 64 KiB (65,536 bytes) of address space (this limit is set by the 16-bit PC and SP registers; the processor does no bounds checking). Offset+address exceeding 0xFFFFF wraps around to 0x00000. Each 64 KiB segment overlaps the next 4,095 segments; each physical address can be denoted by 4,096 segment–offset pairs. This scheme can address only 1 MiB (1024 KiB) of physical memory (and memory-mapped i/o). (Optional
expanded memory hardware can add bank-switched memory under software control.) Intel retroactively named the sole operating mode of these x86 CPU models "
real mode". The
Intel 80286 and later processors add "286
protected mode", which retains 16-bit addressing, and adds segmentation (without paging) and per-segment memory protection. For backward compatibility, all x86 CPUs start up in "real mode", with the same fixed overlapping 64 KiB segments, no memory protection, only 1 MiB physical address space, and some subtle differences (
high memory area,
unreal mode). In order to use its full 24-bit (16 MiB) physical address space and advanced
MMU features, an 80286 or later processor must be switched into "protected mode" by software, usually the operating system or a
DOS extender. If a program does not use the segment registers, or only puts values into them that it receives from the operating system, then identical code can run in real mode or protected mode, but most real-mode software computes new values for the segment registers, breaking this compatibility. The
Intel i386 and later processors add "386
protected mode", which uses 32-bit addressing, retains segmentation, and adds
memory paging. In these processors, the segment table, rather than pointing to a page table for the segment, contains the segment address in
linear memory. When paging is enabled, addresses in linear memory are then mapped to physical addresses using a separate page table. Most operating systems did not use the segmentation capability, opting to keep the base address in all segment registers equal to 0 at all times and provide per-page memory protection and swapping using only paging. Some use the CS register to provide
executable space protection on processors lacking the
NX bit or use the FS or GS registers to access thread-local storage. The
x86-64 architecture does not support segmentation in "
long mode" (64-bit mode). Four of the segment registers: CS, SS, DS, and ES are forced to 0, and the limit to 264. The segment registers FS and GS can still have a nonzero base address. This allows operating systems to use these segments for special purposes such as thread-local storage. ==See also==