IBM System/370

The original System/370 line was announced on June 30, 1970, with first customer shipment of the Models 155 and 165 planned for February 1971 and April 1971 respectively. The 155 first shipped in January 1971. The System/370 architecture incorporated only a small number of changes to the System/360 architecture. These changes included: • 13 new instructions, among which were :* MOVE LONG (MVCL); :* COMPARE LOGICAL LONG (CLCL); ::: thereby permitting operations on up to 2^24-1 bytes (16 MB), vs. the 256-byte limits on the 360's MVC and CLC; :* SHIFT AND ROUND DECIMAL (SRP), which multiplied or divided a packed decimal value by a power of 10, rounding the result when dividing; • optional 128-bit (hexadecimal) floating-point arithmetic, introduced in the System/360 Model 85 • a new higher-resolution time-of-day clock • support for the block multiplexer channel{{sfn|S370 • All of the emulator features were designed to run under the control of the standard operating systems. IBM documented the S/370 emulator programs as integrated emulators. These models had core memory and did not include support for virtual storage, as they lacked a DAT (Dynamic Address Translation) box Logic technology All models of the System/370 used IBM's form of monolithic integrated circuits called MST (Monolithic System Technology) making them third generation computers. MST provided System/370 with four to eight times the circuit density and over ten times the reliability when compared to the previous second generation SLT technology of the System/360. The August 2, 1972 announcement included: • address relocation hardware on all S/370s except the original models 155 and 165 • the new S/370 models 158 and 168, with address relocation hardware • four new operating systems: DOS/VS (DOS with virtual storage), OS/VS1 (OS/360 MFT with virtual storage), OS/VS2 (OS/360 MVT with virtual storage) Release 1, termed SVS (Single Virtual Storage), and Release 2, termed MVS (Multiple Virtual Storage) and planned to be available 20 months later (at the end of March 1974), and VM/370 – the re-implemented CP/CMS Virtual storage had in fact been delivered on S/370 hardware before this announcement: • In June 1971, on the S/370-145 (one of which had to be "smuggled" into Cambridge Scientific Center to prevent anybody noticing the arrival of an S/370 at that hotbed of virtual memory development – since this would have signaled that the S/370 was about to receive address relocation technology). The S/370-145 had an associative memory used by the microcode for the DOS compatibility feature from its first shipments in June 1971; After installation, these models were known as the S/370-155-II and S/370-165-II. IBM wanted customers to upgrade their 155 and 165 systems to the widely sold S/370-158 and -168. These upgrades were surprisingly expensive ($200,000 and $400,000, respectively) and had long ship date lead times after being ordered by a customer; consequently, they were never popular with customers, the majority of whom leased their systems via a third-party leasing company. in the slow adoption of OS/VS2 MVS, not only by customers in general, but for many internal IBM sites as well. Subsequent enhancements Later architectural changes primarily involved expansions in memory (central storage) – both physical memory and virtual address space – to enable larger workloads and meet client demands for more storage. This was the inevitable trend as Moore's Law eroded the unit cost of memory. As with all IBM mainframe development, preserving backward compatibility was paramount. • Operating system specific assist, Extended Control Program Support (ECPS). extended facility and extension features for OS/VS1, MVS and VM. Exploiting levels of these operating systems, e.g., MVS/System Extensions (MVS/SE), reduce path length for some frequent functions. • The Dual Address Space (DAS) facility allows a privileged program to move data between two address spaces without the overhead of allocating a buffer in common storage, moving the data to the buffer, scheduling an SRB in the target address space, moving the data to their final destination and freeing the buffer. IBM introduced DAS in 1981 for the 3033, but later made it available for some 43xx, 3031 and 3032 processors. MVS/System Product (MVS/SP) Version 1 exploited DAS if it was available. • In October 1981, the 3033 and 3081 processors added "extended real addressing", which allowed 26-bit addressing for physical storage (but still imposed a 24-bit limit for any individual address space). This capability appeared later on other systems, such as the 4381 and 3090. • The System/370 Extended Architecture (S/370-XA), first available in early 1983 on the 3081 and 3083 processors, provided a number of major enhancements, including expansion of virtual address spaces from 24-bits to 31-bits, expansion of real addresses from 24 or 26 bits to 31 bits, and a complete redesign of the I/O architecture. • In February 1988, IBM announced the Enterprise Systems Architecture/370 (ESA/370) for enhanced (E) 3090 and 4381 models. It added sixteen 32-bit access registers, more addressing modes, and various facilities for working with multiple address spaces simultaneously. • On September 5, 1990, IBM announced the Enterprise Systems Architecture/390 (ESA/390), upward compatible with ESA/370. Dual address space In 1981, IBM added the dual-address-space facility to System/370. Address spaces are identified by an address-space number (ASN). The ASN contains indices into a two-level table, structured similarly to a two-level page table, with entries containing a presence bit, various fields indicating permissions granted for access to the address space, the starting address and length of the segment table for the address space, and other information. The SET SECONDARY ASN instruction makes the address space identified by a given ASN value the current secondary address space. Extended real addressing The initial System/370 architecture has a 24-bit limit on physical addresses, limiting physical memory to 16 MB. Page table entries have 12 bits of page frame address with 4 KB pages and 13 bits of page frame address with 2 KB pages, so combining a 12-bit page frame address with a 12-bit offset within the page or a 13-bit page frame address with an 11-bit offset within the page produces a 24-bit physical address. The extended real addressing feature in System/370 raises this limit to 26 bits, increasing the physical memory limit to 64 MB. Two reserved bits in the page table entry for 4 KB pages were used to extend the page frame address. The extended real addressing is only available with address translation enabled and with 4 KB pages. ==Series and models==

Models sorted by date introduced (table) The following table summarizes the major S/370 series and models. The second column lists the principal architecture associated with each series. Many models implemented more than one architecture; thus, 308x processors initially shipped as S/370 architecture, but later offered XA; and many processors, such as the 4381, had microcode that allowed customer selection between S/370 or XA (later, ESA) operation. Note also the confusing term "System/370-compatible", which appeared in IBM source documents to describe certain products. Outside IBM, this term would more often describe systems from Amdahl Corporation, Hitachi, and others, that could run the same S/370 software. This choice of terminology by IBM may have been a deliberate attempt to ignore the existence of those plug compatible manufacturers (PCMs), because they competed aggressively against IBM hardware dominance. Models grouped by Model number (detailed) IBM used the name System/370 to announce the following eleven (three-digit) offerings: System/370 Model 115 The IBM System/370 Model 115 was announced March 13, 1973 as "an ideal System/370 entry system for users of IBM's System/3, 1130 computing system and System/360 Models 20, 22 and 25." It was delivered with "a minimum of two (of IBM's newly announced) directly attached IBM 3340 disk drives." Two, three or four directly attached IBM 3333 disk storage units provided "up to 400 million bytes online." Main memory was either 98,304 (96K) or 131,072 (128K) bytes. The 125 was withdrawn on March 9, 1981. System/370 Model 135 The IBM System/370 Model 135 was announced Mar 8, 1971. Options for the 370/135 included a choice of four main memory sizes; IBM 1400 series (1401, 1440 and 1460) emulation was also offered. A "reading device located in the Model 135 console" allowed updates and adding features to the Model 135's microcode. The 135 was withdrawn on October 16, 1979. System/370 Model 138 The IBM System/370 Model 138 which was announced Jun 30, 1976 was offered with either 524,288 (512K) or 1,048,576 (1 MB) of memory. The latter was "double the maximum capacity of the Model 135," which "can be upgraded to the new computer's internal performance levels at customer locations." The 138 was withdrawn on November 1, 1983. System/370 Model 145 The IBM System/370 Model 145 was announced Sep 23, 1970, three months after the 155 and 165 models. As with the option to field-upgrade a 135, a 370/145 could be field-upgraded "at customer locations" to 148-level performance. The upgraded 135 and 145 systems were "designated the Models 135-3 and 145-3." System/370 Model 155 The IBM System/370 Model 155 and the Model 165 were announced Jun 30, 1970, the first of the 370s introduced. Neither had a DAT box; they were limited to running the same non-virtual-memory operating systems available for the System/360. The 155 first shipped in January 1971. (DOS/360 programs under OS/360), 1401/1440/1460 and 1410/7010 and 7070/7074 compatibility features were included, and the supporting integrated emulator programs could operate concurrently with standard System/370 workloads. In August 1972 IBM announced, as a field upgrade only, the IBM System/370 Model 155 II, which added a DAT box. Both the 155 and the 165 were withdrawn on December 23, 1977. System/370 Model 158 The IBM System/370 Model 158 and the 370/168 were announced Aug 2, 1972. It included dynamic address translation (DAT) hardware, a prerequisite for the new virtual memory operating systems (DOS/VS, OS/VS1, OS/VS2). A tightly coupled multiprocessor (MP) model was available, as was the ability to loosely couple this system to another 360 or 370 via an optional channel-to-channel adapter. The 158 and 168 were withdrawn on September 15, 1980. System/370 Model 165 The IBM System/370 Model 165 was described by IBM as "more powerful" In August 1972 IBM announced, as a field upgrade only, the IBM System/370 Model 165 II which added a DAT box. The 165 was withdrawn on December 23, 1977. System/370 Model 168 The IBM System/370 Model 168 included "up to eight megabytes" of main memory, double the maximum of 4 megabytes on the 370/158. a 1975 newsbrief said that IBM boosted the power of the 370/168 again "in the wake of the Amdahl challenge... only 10 months after it introduced the improved 168-3 processor." The 370/168 was not withdrawn until September 1980. System/370 Model 195 The IBM System/370 Model 195 was announced Jun 30, 1970 and, at that time, it was "IBM's most powerful computing system." Its introduction came about 14 months after the announcement of its direct predecessor, the 360/195. Both 195 machines were withdrawn Feb. 9, 1977. IBM 303X The first of the initial high end machines, IBM's 3033, was announced March 25, 1977 and was delivered the following March, at which time a multiprocessor version of the 3033 was announced. IBM described it as "The Big One." IBM noted about the 3033, looking back, that "When it was rolled out on March 25, 1977, the 3033 eclipsed the internal operating speed of the company's previous flagship the System/370 Model 168-3 ..." IBM 308X Three systems comprised the next series of high end machines, IBM's 308X systems: • The 3081 (announced Nov 12, 1980) had 2 CPUs • The 3083 (announced Mar 31, 1982) had 1 CPU • The 3084 (announced Sep 3, 1982) had 4 CPUs Despite the numbering, the least powerful was the 3083, which could be field-upgraded to a 3081; They were announced Feb. 12, 1985, and were configured with two or four CPUs respectively. IBM subsequently announced models 120, 150, 180, 300, 500 and 600 with lower, intermediate and higher capacities; the first digit of the model number gives the number of central processors. Starting with the E models, and continuing with the J and S models, IBM offered Enterprise Systems Architecture/370 (ESA/370), Processor Resource/System Manager (PR/SM) and a set of backward compatible MVS/Enterprise System Architecture (MVS/ESA) software replacing previous products: IBM's offering of an optional vector facility (VF) extension for the 3090 came at a time when Vector processing/Array processing suggested names like Cray and Control Data Corporation (CDC). The 200 and 400 were withdrawn on May 5, 1989. IBM 4300 The first pair of IBM 4300 processors were Mid/Low end systems announced Jan 30, 1979 as "compact (and).. compatible with System/370." The 4331 was subsequently withdrawn on November 18, 1981, and the 4341 on February 11, 1986. Other models were the 4321, 4361 and 4381. The 4361 has "Programmable Power-Off -- enables the user to turn off the processor under program control"; Clones In the 360 era, a number of manufacturers had already standardized upon the IBM/360 instruction set and, to a degree, 360 architecture. Notable computer makers included Univac with the UNIVAC 9000 series, RCA with the RCA Spectra 70 series, English Electric with the English Electric System 4, and the Soviet ES EVM. These computers were not perfectly compatible, nor (except for the Russian efforts) The latter efforts were abandoned and eventually all Japanese efforts focused on the IBM mainframe lines. Some of the era's clones included: ==Architecture details==

IBM documentation numbers the bits from high order to low order; the most significant (leftmost) bit is designated as bit number 0. S/370 also refers to a computer system architecture specification, and is a direct and mostly backward compatible evolution of the System/360 architecture from which it retains most aspects. This specification does not make any assumptions on the implementation itself, but rather describes the interfaces and the expected behavior of an implementation. The architecture describes mandatory interfaces that must be available on all implementations and optional interfaces which may or may not be implemented. Some of the aspects of this architecture are: • Big endian byte ordering • One or more processors with: • 16 32-bit General purpose registers • 16 32-bit Control registers • 4 64-bit Floating-point registers • A 64-bit Program status word (PSW) which describes (among other things) • Interrupt masks • Privilege states • A condition code • A 24-bit instruction address • Timing facilities (Time of day clock, interval timer, CPU timer and clock comparator) • An interruption mechanism, maskable and unmaskable interruption classes and subclasses • An instruction set. Each instruction is wholly described and also defines the conditions under which an exception is recognized in the form of program interruption. • A memory (called storage) subsystem with: • 8 bits per byte • A special processor communication area starting at address 0 • Key controlled protection • 24-bit addressing • Manual control operations that provide: • A bootstrap process (a process called Initial Program Load or IPL) • Operator-initiated interrupts • Resetting the system • Basic debugging facilities • Manual display and modifications of the system's state (memory and processor) • An Input/Output mechanismwhich does not describe the devices themselves Some of the optional features are: • A Dynamic Address Translation (DAT) mechanism that can be used to implement a virtual memory system • Floating point instructions IBM took great care to ensure that changes to the architecture would remain compatible for unprivileged (problem state) programs; some new interfaces did not break the initial interface contract for privileged (supervisor mode) programs. Some examples are ; ECPS:MVS :A feature to enhance performance for the MVS/370 operating systems ;ECPS:VM :A feature to enhance performance for the VM operating systems Other changes were compatible only for unprivileged programs, although the changes for privileged programs were of limited scope and well defined. Some examples are: ;ECPS:VSE :A feature to enhance performance for the DOS/VSE operating system. ;S/370-XA :A feature to provide a new I/O interface and to support 31-bit virtual and physical addressing Great care was taken in order to ensure that further modifications to the architecture would remain compatible, at least as far as non-privileged programs were concerned. This philosophy predates the definition of the S/370 architecture and started with the S/360 architecture. If certain rules are adhered to, a program written for this architecture will run with the intended results on the successors of this architecture. Such an example is that the S/370 architecture specifies that the 64-bit PSW register bit number 32 has to be set to 0 and that doing otherwise leads to an exception. Subsequently, when the S/370-XA architecture was defined, it was stated that this bit would indicate whether the program was a program expecting a 24-bit address architecture or 31-bit address architecture. Thus, most programs that ran on the 24-bit architecture can still run on 31-bit systems; the 64-bit z/Architecture has an additional mode bit for 64-bit addresses, so that those programs, and programs that ran on the 31-bit architecture, can still run on 64-bit systems. However, not all of the interfaces can remain compatible. Emphasis was put on having non control programs (called problem state programs) remain compatible. Thus, operating systems have to be ported to the new architecture because the control interfaces can (and were) redefined in an incompatible way. For example, the I/O interface was redesigned in S/370-XA making S/370 program issuing I/O operations unusable as-is. ==S/370 replacement==

IBM replaced the System/370 line with the System/390 in the 1990s, and similarly extended the architecture from ESA/370 to ESA/390. This was a minor architectural change, and was upwards compatible. In 2000, the System/390 was replaced with the zSeries (now called IBM Z). The zSeries mainframes introduced the 64-bit z/Architecture, the most significant design improvement since the 31-bit transition. All have retained essential backward compatibility with the original S/360 architecture and instruction set. ==GCC and Linux on the S/370==

The GNU Compiler Collection (GCC) had a back end for S/370, but it became obsolete over time and was finally replaced with the S/390 backend. Although the S/370 and S/390 instruction sets are essentially the same (and have been consistent since the introduction of the S/360), GCC operability on older systems has been abandoned. GCC currently works on machines that have the full instruction set of System/390 Generation 5 (G5), the hardware platform for the initial release of Linux/390. However, a separately maintained version of GCC 3.2.3 that works for the S/370 is available, known as GCCMVS. ==I/O evolutions==

I/O evolution from original S/360 to S/370 The block multiplexer channel, previously available only on the 360/85 and 360/195, was a standard part of the architecture. For compatibility it could operate as a selector channel. Block multiplexer channels were available in single byte (1.5 MB/s) and double byte (3.0 MB/s) versions. I/O evolution since original S/370 As part of the DAT announcement, IBM upgraded channels to have Indirect Data Address Lists (IDALs). a form of I/O MMU. Data streaming channels had a speed of 3.0 MB/s over a single byte interface, later upgraded to 4.5 MB/s. Channel set switching allowed one processor in a multiprocessor configuration to take over the I/O workload from the other processor if it failed or was taken offline for maintenance. System/370-XA introduced a channel subsystem that performed I/O queuing previously done by the operating system. The System/390 introduced the ESCON channel, an optical fiber, half-duplex, serial channel with a maximum distance of 43 kilometers. Originally operating at 10 Mbyte/s, it was subsequently increased to 17 Mbyte/s. Subsequently, FICON became the standard IBM mainframe channel; FIbre CONnection (FICON) is the IBM proprietary name for the ANSI FC-SB-3 Single-Byte Command Code Sets-3 Mapping Protocol for Fibre Channel (FC) protocol used to map both IBM's antecedent (either ESCON or parallel Bus and Tag) channel-to-control-unit cabling infrastructure and protocol onto standard FC services and infrastructure at data rates up to 16 Gigabits/sec at distances up to 100 km. Fibre Channel Protocol (FCP) allows attaching SCSI devices using the same infrastructure as FICON. ==See also==