SiP dies can be stacked vertically or tiled horizontally, with techniques like
chiplets or
quilt packaging. SiPs connect the dies with standard off-chip
wire bonds or solder bumps, unlike slightly denser
three-dimensional integrated circuits which connect stacked silicon dies with conductors running through the die using
through-silicon vias. Many different 3D packaging techniques have been developed for stacking many fairly standard chip dies into a compact area. SiPs can contain several chips or dies—such as a specialized
processor,
DRAM,
flash memory—combined with
passive components—
resistors and
capacitors—all mounted on the same
substrate. This means that a complete functional unit can be built in a single package, so that few external components need to be added to make it work. This is particularly valuable in space constrained environments like
MP3 players and
mobile phones as it reduces the complexity of the
printed circuit board and overall design. Despite its benefits, this technique decreases the yield of fabrication since any defective chip in the package will result in a non-functional packaged integrated circuit, even if all other modules in that same package are functional. SiPs are in contrast to the common system on a chip (SoC) integrated circuit architecture which integrates components based on function into a single
circuit die. An SoC will typically integrate a CPU,
graphics and memory interfaces,
hard-disk and
USB connectivity,
random-access and
read-only memories, and secondary storage and/or their controllers on a single die. In comparison an SiP would connect these modules as
discrete components in one or more chip packages or dies. An SiP resembles the common traditional
motherboard-based
PC architecture, as it separates components based on function and connects them through a central interfacing circuit board. An SiP has a lower grade of integration in comparison to an SoC. Hybrid integrated circuits (HICs) are somewhat similar to SiPs, however they tend to handle analog signals whereas SiPs usually handle digital signals, because of this HICs use older or less advanced technology (tend to use single layer circuit boards or substrates, not use die stacking, do not use flip chip or BGA for connecting components or dies, use only wire bonding for connecting dies or Small outline integrated circuit packages, use Dual in-line packages, or Single in-line packages for interfacing outside the Hybrid IC instead of BGA, etc.). SiP technology is primarily being driven by early market trends in
wearables, mobile devices and the
Internet of things which do not demand the high numbers of produced units as in the established consumer and business SoC market. As the Internet of things becomes more commonplace in the SiP market, advances in SiP packaging design enable
microelectromechanical (MEMS) sensors to be integrated on a separate die and control connectivity. SiP solutions may require multiple
packaging technologies, such as
flip chip,
wire bonding,
wafer-level packaging, through-silicon vias (TSVs), chiplets and more. == Suppliers ==