The LARC was a decimal mainframe computer with 60
bits per
word. It used
bi-quinary coded decimal arithmetic with five bits per
digit (see below), allowing for 11-digit
signed numbers.
Instructions were 60 bits long, one per word. The basic configuration had 26 general-purpose
registers, which could be expanded to 99. The general-purpose registers had an access time of one microsecond. LARC weighed about . The basic configuration had one
Computer and LARC could be expanded to a multiprocessor with a second
Computer. The
Processor is an independent CPU (with a different instruction set from the
Computers) and provides control for 12 to 24
magnetic drum storage units, four to forty
UNISERVO II tape drives, two electronic page recorders (a 35mm film camera facing a cathode-ray tube), one or two high-speed printers, and a high-speed
punched card reader. The LARC used
core memory banks of 2500 words each, housed four banks per memory cabinet. The basic configuration had eight banks of core (two cabinets), 20,000 words. The memory could be expanded to a maximum of 39 banks of core (ten cabinets with one empty bank), 97,500 words. The core memory had one
parity bit on each digit for error checking, resulting in 60 bits per memory word. The core memory had an access time of 8
microseconds and a cycle time of 4 microseconds. Each bank operated independently and could begin a new access in any 4-microsecond cycle when it was not already busy. By properly interleaving accesses to different banks the memory could sustain an effective access time of 4 microseconds on each access (e.g., instruction access in one bank data in another). The data transfer bus connecting the two
Computers and the
Processor to the core memory was multiplexed to maximize throughput; every 4-
microsecond bus cycle was divided into eight 500-nanosecond time slots: •
Processor - instructions and data •
Computer 1 - instructions •
Computer 2 - data • I/O DMA
Synchronizer - data • Not Used •
Computer 2 - instructions •
Computer 1 - data • I/O DMA
Synchronizer - data The core memory system enforces a system of interlocks and priorities to avoid simultaneous access of the same memory bank by multiple sections of the system (the
Computers,
Processor, and I/O DMA
Synchronizers) without conflicts or
deadlocks. A memory bank is unavailable for one 4-microsecond cycle after being addressed by any section of the system. If another section attempts to address the same memory bank during this time, it is locked out and must wait, then try again in the next 4-microsecond cycle. To prevent deadlocks and timeouts in the I/O system the following priorities are enforced: • I/O DMA
Synchronizer - highest •
Processor •
Computers - lowest If a higher-priority section is locked out in one 4-microsecond cycle, when it tries again in the next 4-microsecond cycle, all lower-priority sections are prevented from beginning a new cycle on that memory bank until the higher-priority section has completed its access. The LARC's Computers wrote lists of
Summary Orders in memory for the Processor to read and interpret by the
Processor Control Program (written and supplied by UNIVAC with each system), to request needed I/O. The LARC was built using
surface-barrier transistors, which were already obsolete by the time the first system was delivered. The LARC was a very fast computer for its time. Its addition time was 4 microseconds, multiplication time was 8 microseconds, and the division time was 28 microseconds. It was the fastest computer in 196061, until the
IBM 7030 took the title. ==LARC one-digit numeric code==