The ARM Cortex-A78 is the successor to the
ARM Cortex-A77. It can be paired with the
ARM Cortex-X1 and/or
ARM Cortex-A55 CPUs in a
DynamIQ configuration to deliver both performance and efficiency. The processor also claims as much as 50% energy savings over its predecessor. and efficiency improvements to instruction schedulers,
register renaming structures, and the
re-order buffer. L2 cache is available up to 512 KB and has double the bandwidth to maximize the performance, while the shared L3 cache is available up to 4 MB, double that of previous generations. A Dynamic Shared Unit (DSU) also allows for an 8 MB configuration with the
ARM Cortex-X1. == Variants ==