Many failures produce
hot electrons. These are observable under an optical microscope, as they generate near-
infrared photons detectable by a
CCD camera.
Latchups can be observed this way. • Laser marking of plastic-encapsulated packages may damage the chip if glass spheres in the packaging line up and direct the laser to the chip. Sometimes, circuit tolerances can make erratic behaviour difficult to trace; for example, a weak driver transistor, a higher series resistance and the capacitance of the gate of the subsequent transistor may be within tolerance but taken together can significantly increase signal
propagation delay. These can manifest only at specific environmental conditions, high clock speeds, low power supply voltages, and sometimes specific circuit signal states; significant variations can occur on a single die. • Degradation of IDSS by gate sinking and
hydrogen poisoning. This failure is the most common and easiest to detect. • Degradation in gate
leakage current. This occurs in accelerated life tests or high temperatures and is suspected to be caused by surface-state effects. • Degradation in
pinch-off voltage. This is a common failure mode for gallium arsenide devices operating at high temperature, and primarily stems from semiconductor-metal interactions and degradation of gate metal structures, with hydrogen being another reason. It can be hindered by a suitable
barrier metal between the contacts and gallium arsenide. • Increase in drain-to-source resistance. It is observed in high-temperature devices, and is caused by metal-semiconductor interactions, gate sinking and ohmic contact degradation.
Metallisation failures Metallisation failures are more common and serious causes of FET transistor degradation than material processes;
amorphous materials have no grain boundaries, hindering interdiffusion and corrosion. Examples of such failures include: •
Electromigration moving atoms out of active regions, causing dislocations and point defects acting as nonradiative recombination centers, producing heat. This may occur with aluminium gates in
MESFETs with
RF signals, causing erratic drain current; electromigration in this case is called
gate sinking. This issue does not occur with gold gates. • Oxide breakdown occurring at field strengths above 6–10 MV/cm. • Junction damage manifests as reverse-bias leakage that increases to the point of shorting. • Metallisation and polysilicon burnout, where damage is limited to metal and
polysilicon interconnects, thin film resistors and diffused resistors. • Charge injection, where hot carriers generated by avalanche breakdown are injected into the oxide layer. Catastrophic ESD failure modes include: • Junction burnout, where a conductive path forms through the junction and shorts it • Metallisation burnout, where the melting or vaporizing of a part of the metal interconnect interrupts it • Oxide punch-through, formation of a conductive path through the insulating layer between two conductors or semiconductors; the
gate oxides are thinnest and therefore most sensitive. The damaged transistor shows a low-ohmic junction between the gate and drain terminals. A parametric failure only shifts the device parameters and may result in
stress testing failure. Latent ESD failure modes occur in a delayed fashion and include: • Insulator damage by weakening of the insulator structures. • Junction damage by lowering minority carrier lifetimes, increasing forward-bias resistance and increasing reverse-bias leakage. • Metallisation damage by conductor weakening. Catastrophic failures require the highest discharge voltages, are the easiest to test for and are rarest to occur. Parametric failures occur at intermediate discharge voltages and occur more often, with latent failures the most common. For each parametric failure, there are 4–10 latent ones. Modern
VLSI circuits are more ESD-sensitive, with smaller features, lower capacitance and higher voltage-to-charge ratio. Silicon deposition of the conductive layers makes them more conductive, reducing the ballast resistance that has a protective role. The
gate oxide of some
MOSFETs can be damaged by 50 volts of potential, the gate isolated from the junction and potential accumulating on it causing extreme stress on the thin dielectric layer; stressed oxide can shatter and fail immediately. The gate oxide itself does not fail immediately but can be accelerated by
stress induced leakage current, the oxide damage leading to a delayed failure after prolonged operation hours; on-chip capacitors using oxide or nitride dielectrics are also vulnerable. Smaller structures are more vulnerable because of their lower
capacitance, meaning the same amount of charge carriers charges the capacitor to a higher voltage. All thin layers of dielectrics are vulnerable; hence, chips made by processes employing thicker oxide layers are less vulnerable. Current-induced failures are more common in bipolar junction devices, where Schottky and PN junctions are predominant. The high power of the discharge, above 5 kilowatts for less than a microsecond, can melt and vaporise materials. Thin-film resistors may have their value altered by a discharge path forming across them, or having part of the thin film vaporized; this can be problematic in precision applications where such values are critical. Newer CMOS
output buffers using lightly doped
silicide drains are more ESD sensitive; the N-channel driver usually suffers damage in the oxide layer or n+/p well junction. This is caused by current crowding during the snapback of the parasitic NPN transistor. In P/NMOS totem-pole structures, the NMOS transistor is almost always the one damaged. The structure of the junction influences its ESD sensitivity; corners and defects can lead to current crowding, reducing the damage threshold. Forward-biased junctions are less sensitive than reverse-biased ones because the
Joule heat of forward-biased junctions is dissipated through a thicker layer of the material, as compared to the narrow depletion region in reverse-biased junction. ==Passive element failures==