Microarchitecture and system-level design The initial chip design process begins with system-level design and microarchitecture planning. Within IC design companies, management and often analytics will draft a proposal for a design team to start the design of a new chip to fit into an industry segment. Upper-level designers will meet at this stage to decide how the chip will operate functionally. This step is where an IC's functionality and design are decided. IC designers will map out the functional requirements, verification testbenches, and testing methodologies for the whole project, and will then turn the preliminary design into a system-level specification that can be simulated with simple models using languages like C++ and MATLAB and emulation tools. For pure and new designs, the system design stage is where an
instruction set and operation are planned out, and in most chips, existing instruction sets are modified for newer functionality. Design at this stage often involves statements such as
encodes in the MP3 format or
implements IEEE floating-point arithmetic. At later stages in the design process, each of these innocent-looking statements expands to hundreds of pages of textual documentation.
RTL design Upon agreement of a system design, RTL designers then implement the functional models in a hardware description language like
Verilog,
SystemVerilog, or
VHDL. Using digital design components like adders, shifters, and state machines as well as computer architecture concepts like pipelining, superscalar execution, and
branch prediction, RTL designers will break a functional description into hardware models of components on the chip working together. Each of the simple statements described in the system design can easily turn into thousands of lines of
RTL code, which is why it is extremely difficult to verify that the RTL will do the right thing in all the possible cases that the user may throw at it. To reduce the number of functionality bugs, a separate hardware verification group will take the RTL and design testbenches and systems to check that the RTL actually is performing the same steps under many different conditions, classified as the domain of
functional verification. Many techniques are used, none of them perfect but all of them useful – extensive
logic simulation,
formal methods,
hardware emulation,
lint-like code checking,
code coverage, and so on. Verification such as that done by emulators can be carried out in FPGAs or special processors, and emulation replaced simulation. Simulation was initially done by simulating logic gates in chips, but later on, RTLs in chips were simulated instead. Simulation is still used when creating analog chip designs. Prototyping platforms are used to run software on prototypes of the chip design while it is under development using FPGAs but are slower to iterate on or modify and can't be used to visualize hardware signals as they would appear in the finished design. A tiny error here can make the whole chip useless, or worse. The famous
Pentium FDIV bug caused the results of a division to be wrong by at most 61 parts per million, in cases that occurred very infrequently. No one even noticed it until the chip had been in production for months. Yet
Intel was forced to offer to replace, for free, every chip sold until they could fix the bug, at a cost of $475 million (US).
Physical design RTL is only a behavioral model of the actual functionality of what the chip is supposed to operate under. It has no link to a physical aspect of how the chip would operate in real life at the materials, physics, and electrical engineering side. For this reason, the next step in the IC design process,
physical design stage, is to map the RTL into actual geometric representations of all electronic devices, such as capacitors, resistors, logic gates, and transistors that will go on the chip. The main steps of physical design are listed below. In practice, there is not a straightforward progression - considerable iteration is required to ensure all objectives are met simultaneously. This is a difficult problem in its own right, called
design closure. •
Logic synthesis: The RTL is mapped into a gate-level netlist in the target technology of the chip. •
Floorplanning: The RTL of the chip is assigned to gross regions of the chip, input/output (I/O) pins are assigned and large objects (arrays, cores, etc.) are placed. •
Placement: The gates in the netlist are assigned to non-overlapping locations on the die area. • Logic/placement refinement: Iterative logical and placement transformations to close performance and power constraints. •
Clock insertion: Clock signal wiring is (commonly,
clock trees) introduced into the design. •
Routing: The wires that connect the gates in the netlist are added. • Postwiring optimization: Performance (
timing closure), noise (
signal integrity), and yield (
design for manufacturability) violations are removed. •
Design for manufacturability: The design is modified, where possible, to make it as easy and efficient as possible to produce. One common improvement, for example, is to make the areal density of features as uniform as possible across the chip. This is achieved by adding extra vias or adding dummy metal/diffusion/poly layers wherever possible while complying to the design rules set by the foundry. • Final checking: Since errors are expensive, time-consuming and hard to spot, extensive error checking is the rule,
making sure the mapping to logic was done correctly, and
checking that the manufacturing rules were followed faithfully. • Chip finishing with tapeout and mask generation: the design data is turned into
photomasks in
mask data preparation. == Analog design ==