Packaging Meteor Lake is a 64-bit
x86 CPU architecture designed around low power operation and increased power efficiency over Raptor Lake. It is the first Intel microarchitecture to utilize a disaggregated multi-chip module (MCM) approach rather than using large monolithic silicon dies. Previously, in June 2017, Intel had derided
AMD's disaggregated chiplet approach in their
Ryzen and
Epyc processors as using "glued-together" dies. The first advantage of using smaller
dies in an MCM is how it brings better modularity and fabricating smaller dies increases silicon yield rates as more dies can be fitted onto a single 300mm
wafer. As a result of greater yields, the use of multiple pre-tested components in an MCM removes the need for
binning an entire assembled CPU as is the case with monolithic dies. For example, Raptor Lake desktop silicon with defective graphics is binned into F SKUs with the integrated graphics disabled so they can still be sold while non-F SKUs have their integrated graphics enabled. Instead, Intel can assemble Meteor Lake CPUs using multiple pieces of fully functional silicon while any silicon wafer defects can be discarded entirely. The second advantage is greater flexibility in the use of process nodes. The various dies in an MCM can be fabricated on different nodes depending on their use case. Certain functions like SRAM and general I/O do not linearly scale as logic does with advancements in process node. For example, an I/O die can use a cheaper, more mature process like
TSMC's
N6 while the CPU die can use a more expensive, advanced node like
N5 or
N3 for greater power efficiency and frequency.
Process technology Due to its MCM construction, Meteor Lake can take advantage of different process nodes that are best suited to the use case. Meteor Lake is built using four different fabrication nodes, including both Intel's own nodes and external nodes outsourced to fabrication competitor
TSMC. The "Intel 4" process used for the CPU tile is the first process node in which Intel is utilising
extreme ultraviolet (EUV) lithography, which is necessary for creating nodes 7 nm and smaller. The interposer base tile is fabricated on Intel's 22FFL, or "Intel 16", process. The 22FFL (FinFET Low-power) node, first announced in March 2017, was designed for inexpensive low power operation. The interposer base tile is designed to connect tiles together and allow for die-to-die communication which does not require the most advanced, expensive nodes so an older, inexpensive node can be used instead.
Compute tile Meteor Lake's CPU compute tile features up to 6 Redwood Cove P-cores and 8 Crestmont E-cores. Each Redwood Cove P-core features SMT with two threads per core while Crestmont E-cores are limited to one thread per core. The 8 total Crestmont E-cores are organized into two 4-core clusters with shared L2 and L3 caches for each cluster. Each Crestmont E-core cluster has 2MB of L2 cache, the same as a Gracemont E-core cluster. Crestmont maintains the same 6-wide out-of-order core design as Gracemont with enhancements to its pipeline. The branch target buffer in Crestmont gets a boost from 5120 entries to 6144 entries. Intel claims that Crestmont achieves a 3% IPC increase due to the addition of Vector Neural Network Instructions (VNNI) instructions support for AI workloads but Crestmont E-cores still lack support for
AVX-512 instructions due to lack of
AVX10 support. Testing of Meteor Lake's new Redwood Cove P-cores actually showed an IPC regression in single-core workloads over the previous generation Raptor Cove core. Meteor Lake's compute tile is fabricated on the
Intel 4 node which Intel claims brings a 20% increase in power efficiency and twice the area density for logic over
Intel 7. The CPU tile measures around 8.9mm × 8.3mm in dimensions, giving a total die size of 73.87mm2. Much like the Xe-HPG variant, each Xe-LPG core contains a 192KB L1 cache shared between all 16 XVEs. The 8 Xe-LPG cores have access to a 4MB global L2 cache. However, what the graphics tile is missing from the Alchemist architecture are Xe Matrix Extensions (XMX) units. XMX units perform in-silicon AI acceleration, similar to
Nvidia's Tensor cores. The lack of XMX units means that the Xe-LPG core instead uses DP4a instructions in line with Microsoft Shader Model 6.4. Meteor Lake's graphics capabilities are greatly increased over the previous generation UHD and Iris Xe integrated graphics in Raptor Lake. Intel claims that Meteor Lake's GPU achieves a 2x increase in performance-per-watt over the Iris Xe graphics featured in Alder Lake and Raptor Lake processors. There is full support included for the
DirectX 12 Ultimate graphics API and Intel's XeSS upscaler, an alternative to
Nvidia's DLSS and
AMD's FSR. Intel claims that the graphics tile in Meteor Lake can give a similar level of performance to discrete graphics. Tom Petersen claimed that Meteor Lake's integrated graphics performance is "not that far from a [RTX] 3050". Intel demonstrated
Dying Light 2 running on Meteor Lake's integrated graphics at 1080p with XeSS performance mode upscaling from 720p. A hardware listing from
Dell confirmed that in order to fully make use of the integrated Arc graphics, the system must be configured with at least 16GB of memory running in dual-channel mode. Not meeting the minimum memory requirements means that the system will report using lower performance "Intel Graphics" instead of "Arc" graphics.
SoC tile Meteor Lake's SoC tile serves as the always-active central tile that communicates with other tiles like the CPU and GPU tiles. The SoC tile is fabricated using
TSMC's
N6 node as it is more cost effective. The SoC's low power E-cores are limited in frequency to 2.5GHz compared to the 3.8GHz of the E-cores. These cores are designed to handle deep background tasks for laptops in idle or sleep mode. All deep background tasks being handled by two Crestmont E-cores in the SoC tile allows the inactive CPU tile to be turned off entirely.
Media engine Rather than the media engine be located on the GPU tile, it is instead placed on the SoC tile so that the GPU tile does not need to be turned on when decoding video or using a display output. This enables greater power efficiency as the GPU tile is not always active while the system is at idle or under light loads like video playback. There is support added in the media engine for
AV1 hardware encoding up to
8K video with 10-bit color depth. Four display pipes provide support for
HDMI 2.1 and
DisplayPort 2.1 UHBR20 display outputs with the ability to drive up to four
4K 60Hz
HDR monitors at once or one 8K
HDR monitor.
1080p and
1440p monitors can be supported with a refresh rate up to 360Hz.
Neural Processing Unit (NPU) Meteor Lake features a Neural Processing Unit (NPU) to provide integrated AI capabilities. Meteor Lake's NPU, which is marketed as Intel AI Boost, uses two Movidius 32-bit LEON microcontrollers called 'LeonRT' for processing host commands and 'LeonNN' for low level hardware scheduling. It is capable of executing 1 FP16 or 2 INT8 operations per cycle but the NPU's Data Processing Unit (DPU) cannot use FP32 data. The 4K (4096)
MACs operating at up to 1.4GHz can perform up to 11 TOPS Meteor Lake's NPU allows AI acceleration and neural processing like
Stable Diffusion to be done locally, on silicon rather than in the
cloud. The benefit of running such functions locally is that it provides greater
privacy and does not require an internet connection or paying a fee to a third party for using their server computing power. AI neural engines were previously included by
Apple on their
ARM-based
M1 SoCs and by AMD with the integrated Ryzen AI engine on their Ryzen 7040 series mobile processors codenamed "Phoenix".
I/O extender tile The I/O extender tile is the smallest tile in Meteor Lake, fabricated on
TSMC's
N6 node. It provides scalable I/O blocks, which is primarily to offer additional connectivity to that of the SoC tile, such as
PCIe 5.0 lanes. The I/O tile can be scaled depending on the number of PCIe lanes needed and the speed they operate at.
Foveros interposer base tile Meteor Lake uses a passive silicon interposer placed underneath its tiles as an interconnect. The tiles are placed on top of the interposer and are bonded to the interposer using
through-silicon via (TSV) connections through the two vertically stacked pieces of silicon. The TSVs connect the dies with a 36 μm pitch to enable die-to-die communication. Placing logic dies on top of an interposer requires TSVs to connect the top dies through the interposer onto the package. By contrast,
AMD's chiplet approach uses multiple pieces of silicon that are interconnected via traces on the package substrate. The benefit of AMD's approach is its cost-effective scalability where the same CCDs can be used in both their
Ryzen desktop and
Epyc server processors. AMD's Infinity Fabric approach comes with the drawbacks of increased
latency and using additional power for die-to-die communication at around 1.5 picojoules per bit. The compute tile contained heterogenous cores with one
Sunny Cove big core and four
Tremont small cores, predecessors to Meteor Lake's Redwood Cove and Crestmont cores. Lakefield was discontinued in July 2021. == Features ==