SHAKTI (microprocessor)

Shakti processors are based on the RISC-V instruction set architecture (ISA). The processors are designed to have either 22 nm process fin field-effect transistor (FinFET) or 180 nm process complementary metal–oxide–semiconductor (CMOS) technology nodes depending on the manufacturing semiconductor fabrication plant (foundry). Shakti plans a family of processors as part of its road-map, catering to different segments of the market. They have been broadly categorized into "Base Processors", "Multi-Core Processors" and "Experimental Processors". The E and C-classes core are for the Internet of things (IoT), embedded system, and desktop computer markets. The processor design is free of any royalty and is open-source licensed under the modified BSD License. E-class and C-class cores are both implemented in Bluespec SystemVerilog (BSV) language, a Haskell dialect. The Shakti project aims to build 6 variants of processors based on the RISC-V ISA. == Base classes of processors ==

E-class The E-class are 32- and 64-bit microcontrollers able to support all extensions of the RISC-V ISA, for low-power and low computer applications. The E-class is an in-order 3 stage pipeline having an operational frequency of less than 200 MHz on silicon. It is positioned against ARM's M-class (Cortex-M series) cores. It can run real-time operating systems like FreeRTOS, Zephyr, and eChronos. Market segments of E-class processor support smart cards, IoT devices, motor controls, and robotic platforms. E-arty35T is a SoC built around E-class. The E-arty35T SoC is a single-chip 32-bit E-class microcontroller with 128kB RAM. It has 32 general-purpose input/output (GPIO) pins (out of which upper 16 GPIO pins are dedicated to onboard LEDs and switches), a platform level interrupt controller (PLIC), a Counter, 2 Serial Peripheral Interface (SPI), 2 universal asynchronous receiver-transmitter (UART), 1 Inter-Integrated Circuit (I²C), 6 pulse-width modulator (PWM) and an inbuilt Xilinx analog-to-digital converter (X-ADC). C-class The C-class is a 64-bit controller class of processor, for mid-range embedded application. The core is highly optimized, 6-stage in-order design with MMU support and the capability to run operating systems like Linux and Sel4. It is extremely configurable with the support of the standard RV64GC ISA extensions. It is for mid-range compute systems running over 200-800 MHz. It can also be customized up to 2 GHz. It is positioned against ARM's Cortex A35/A55. The application domain of this class ranges from embedded systems, motor-control, IoT, storage, industrial applications to low-cost high-performance Linux based applications such as networking, gateways etc. I-class The I-class is a 64-bit processor for the compute, mobile, storage, and networking platforms. Its features include out-of-order execution, multithreading, aggressive branch prediction, non-blocking caches and deep instruction pipelining stages. The operational clock frequency of this processor is 1.5-2.5 GHz. As of April 2020, the team was working on implementing atomics, memory dependence prediction, instruction window/scheduler optimizations, implementation of some functional units, performance analysis/projections, optimizations to meet first-cut target frequency on 1 GHz on 22 nm processor. == Multicore processors ==

M-class A mobile class processor with a maximum of eight cores, the cores being a combination of C and I class cores. The M-class processors are for general-purpose compute, low-end server and mobile applications. The operation frequency ranges up to 2.5 GHz. It supports large issue size, quad-threaded and optional NoC fabric. The M-class processors are optimized for various power and performance goals. S-class The S-Class is a 64-bit superscalar, multi-threaded variant for desktop and enterprise server uses. Its supports 2–16 cores with a clock frequency of about 1.2–3 GHz. H-class The H-class is a 64-bit processor for highly parallel enterprise, HPC, and analytics applications. The cores can be a combination of C or I class, single-thread performance driving the core choice. The H-class has up to 128 cores with multiple accelerators per core. == Experimental processors ==

These are experimental/research projects which focus on developing a high security and fault tolerant processor. T-class The T-class is aimed to provide additional hardware support for securing information from memory-based attacks. Its design focuses on a unified hardware framework for mitigating spatial and temporal memory attacks. F-class The F-class is a fault-tolerant version of the base class processor. Features include redundant compute blocks (like DMR and TMR), temporal redundancy modules to detect permanent faults, lock-step core configurations, fault localization circuits, ECC for critical memory blocks and redundant bus fabrics. == Tapeouts ==

Two C-class processors (codenamed RIMO and Risecreek) and one E-class processor (Moushik) have been taped-out so far. RIMO RIMO is the code name of the Shakti C-class based SoC that has been taped-out at Semi-Conductor Laboratory at Mohali using 180 nm process technology. The 144 sq.mm. chip has been tested to operate at a frequency of up to 70 MHz. The chip has been packaged on a 208-pin Ceramic Quad Flat Pack (CQFP). IRIS IIT Madras and ISRO Inertial Systems Unit successfully designed and booted a 64-bit IRIS (Indigenous RISC-V Controller for Space Applications) chip based on the SHAKTI baseline processor in February 2025. The chip configuration takes into account the processing power and functional needs of the devices and sensors utilized in ISRO missions. To improve dependability, fault-tolerant internal memory were interfaced with the SHAKTI core. IRIS is the third chip produced by SCL using 180 nm process, following RIMO in 2018 and MOUSHIK in 2020. The chip packaging process was handled by Tata Advanced Systems. Syrma SGS finished the installation and assembly, while PCB Power developed the motherboard. Chip design, fabrication, packaging, motherboard design and fabrication, software, and boot were all completed in India validating the presence of expertise and complete semiconductor ecosystem. To validate chip performance, a flight test is scheduled. == Features of RIMO and Risecreek ==

Some of the features of RIMO and Risecreek are as follows: • In-order 5 stage 64-bit microcontroller supporting the entire stable RISC-V ISA(RV64IMAFD). • Compatible with privilege spec (v1.10) of RISC-V ISA and supports the sv39 virtualisation scheme. • Includes a branch predictor with a Return-Address-Stack. • Pipelined IEEE-754 compliant single and double-precision floating point units and Multi-channel direct memory access (DMA) support. • Peripherals like 2 x I²C, 2 x UART, 2 x QSPI, a debugger, a 256KB tightly coupled memory, 32-bit GPIOs and an expansion bus that can be connected to a field-programmable gate array (FPGA). == Development boards ==

There are development boards for both E and C-class of processors. The details on the board support for different classes of processors are given below. E-arty35T • E-arty35Tis a SoC based on Shakti E class [14]. • E-arty35Tis supported on Artix 7 35T board. • It has an abridged version of 32-bit E class. It includes I, M, A and C. C-arty100T • C-arty100Tis a SoC based on Shakti C-class. • C-arty100Tis supported on Artix 7 100T board. • It has an abridged version of 64-bit C-class. It includes I, M, A, F, D and C. == Commercial support ==

Altair Engineering from July 2021, included E-Class processor in its embedded system firmware support portfolio for its global customers. == Swadeshi Microprocessor Challenge ==

On December 7, 2021, the Ministry of Electronics and Information Technology honored the Swadeshi Microprocessor Challenge winners. At different phases of the challenge, participants get up to ₹4.40 crore in funding for the development of a hardware prototype and the incubation of a start-up by participating teams. C-DAC and IIT Madras made accessible for the challenge their SoCs, THEJAS32 and THEJAS64, based on VEGA 32-bit and 64-bit processors and Shakti. The participating teams successfully implemented the SoCs in a variety of designs. Ten teams became victorious from the 30 finalist teams. Team VEGA FCS FT (AI drone), received a ₹35 lakh cheque for their drone application; second-place winners, Team HWDL, received ₹30 lakh for FM Radio Data System Utilities; and third-place winners, Cytox, received ₹25 lakh for their cell count project. Each of the other teams received a check for ₹20 lakh for sharing fourth place. The teams are Astrek Innovations (lower limb exosuit for disabled), Team 6E Resources (remote monitoring and optimization of sewage treatment plant), Team Anshashodhak (unique calibration system for nuclear spectroscopy applications), Team Quicproc (wireless maternal monitoring system), Team Avrio Energy (AI Energy Meter with intelligence at edge and deep learning), and Team JayHawks (anti-theft geofencing based locking system). Thirty finalist teams of the Swadeshi Microprocessor Challenge have been awarded incubation support by Maker Village, the largest electronic system design and production center in India. == See also ==