Background The
Larrabee microarchitecture (in development since 2006) introduced very wide (512-bit)
SIMD units to an
x86 architecture based processor design, extended to a
cache-coherent multiprocessor system connected via a ring bus to memory; each core was capable of four-way multithreading. Due to the design being intended for GPU as well as general purpose computing, the Larrabee chips also included specialised hardware for texture sampling. The project to produce a retail GPU product directly from the Larrabee research project was terminated in May 2010. Another contemporary Intel research project implementing x86 architecture on a many-multicore processor was the '
Single-chip Cloud Computer' (prototype introduced 2009), a design mimicking a
cloud computing computer datacentre on a single chip with multiple independent cores: the prototype design included 48 cores per chip with hardware support for selective frequency and voltage control of cores to maximize energy efficiency, and incorporated a
mesh network for inter-chip messaging. The design lacked cache-coherent cores and focused on principles that would allow the design to scale to many more cores. The
Teraflops Research Chip (prototype unveiled 2007) is an experimental 80-core chip with two
floating-point units per core, implementing a 96-bit
VLIW architecture instead of the x86 architecture. The project investigated intercore communication methods, per-chip power management, and achieved 1.01
TFLOPS at 3.16 GHz consuming 62 W of power.
Knights Ferry Intel's Many Integrated Core (MIC) prototype board, named
Knights Ferry, incorporating a processor codenamed
Aubrey Isle was announced 31 May 2010. The product was stated to be a derivative of the
Larrabee project and other Intel research including the
Single-chip Cloud Computer. The development product was offered as a PCIe card with 32 in-order cores at up to 1.2 GHz with four threads per core, 2 GB GDDR5 memory, and 8 MB coherent L2 cache (256 KB per core with 32 KB L1 cache), and a power requirement of ≈300 W, Single-board performance has exceeded 750 GFLOPS. Initial developers included
CERN,
Korea Institute of Science and Technology Information (KISTI) and
Leibniz Supercomputing Centre. Hardware vendors for prototype boards included IBM, SGI, HP, Dell and others.
Knights Corner The
Knights Corner product line is made at a 22 nm process size, using Intel's
Tri-gate technology with more than 50 cores per chip, and is Intel's first many-cores commercial product. In June 2011,
SGI announced a partnership with Intel to use the MIC architecture in its high-performance computing products. In September 2011, it was announced that the
Texas Advanced Computing Center (TACC) will use Knights Corner cards in their 10-petaFLOPS "Stampede" supercomputer, providing 8 petaFLOPS of compute power. According to "Stampede: A Comprehensive Petascale Computing Environment" the "second-generation Intel (Knights Landing) MICs will be added when they become available, increasing Stampede's aggregate peak performance to at least 15 PetaFLOPS." On 15 November 2011, Intel showed an early silicon version of a Knights Corner processor. On 5 June 2012, Intel released open source software and documentation regarding Knights Corner. On 18 June 2012, Intel announced at the 2012 Hamburg
International Supercomputing Conference that
Xeon Phi will be the
brand name used for all products based on their Many Integrated Core architecture. In June 2012,
Cray announced it would be offering 22 nm 'Knight's Corner' chips (branded as 'Xeon Phi') as a co-processor in its 'Cascade' systems. In June 2012, ScaleMP announced a virtualization update allowing Xeon Phi as a transparent processor extension, allowing legacy
MMX/
SSE code to run without code changes. An important component of the Intel Xeon Phi coprocessor's core is its vector processing unit (VPU). The VPU features a novel 512-bit SIMD instruction set, officially known as Intel Initial Many Core Instructions (Intel IMCI). Thus, the VPU can execute 16
single-precision (SP) or 8
double-precision (DP) operations per cycle. The VPU also supports Fused Multiply-Add (FMA) instructions and hence can execute 32 SP or 16 DP floating point operations per cycle. It also provides support for integers. The VPU also features an Extended Math Unit (EMU) that can execute operations such as reciprocal, square root, and logarithm, thereby allowing these operations to be executed in a vector fashion with high bandwidth. The EMU operates by calculating polynomial approximations of these functions. On 12 November 2012, Intel announced two Xeon Phi coprocessor families using the 22 nm process size: the Xeon Phi 3100 and the Xeon Phi 5110P. The Xeon Phi 3100 will be capable of more than 1 teraFLOPS of
double-precision floating-point instructions with 240 GB/s memory bandwidth at 300 W. The basis of the Intel MIC architecture is to leverage x86 legacy by creating an x86-compatible multiprocessor architecture that can use existing parallelization software tools.
OpenCL,
Cilk/
Cilk Plus and specialised versions of Intel's Fortran, C++ and math libraries. Design elements inherited from the Larrabee project include x86 ISA, 4-way
SMT per core, 512-bit SIMD units, 32 KB L1 instruction cache, 32 KB L1 data cache, coherent L2 cache (512 KB per core), and ultra-wide ring bus connecting processors and memory. The Knights Corner 512-bit SIMD instructions share many intrinsic functions with the AVX-512 extension. The instruction set documentation is available from Intel under the extension name of KNC.
Knights Landing Code name for the second-generation MIC architecture product from Intel. using
LGA 3647 socket supporting up to 384 GB of "far" DDR4 2133 RAM and 8–16 GB of stacked "near" 3D
MCDRAM, a version of the
Hybrid Memory Cube. Each core has two 512-bit vector units and supports
AVX-512 SIMD instructions, specifically the Intel AVX-512 Foundational Instructions (AVX-512F) with Intel AVX-512 Conflict Detection Instructions (AVX-512CD), Intel AVX-512 Exponential and Reciprocal Instructions (AVX-512ER), and Intel AVX-512 Prefetch Instructions (AVX-512PF). Support for IMCI has been removed in favor of AVX-512. The
National Energy Research Scientific Computing Center announced that Phase 2 of its newest supercomputing system "Cori" would use Knights Landing Xeon Phi coprocessors. On 20 June 2016, Intel launched the Intel Xeon Phi product family x200 based on the Knights Landing architecture, stressing its applicability to not just traditional simulation workloads, but also to
machine learning. The model lineup announced at launch included only Xeon Phi of bootable form-factor, but two versions of it: standard processors and processors with integrated Intel
Omni-Path architecture fabric. The latter is denoted by the suffix F in the model number. Integrated fabric is expected to provide better latency at a lower cost than discrete high-performance network cards. The
PCIe based co-processor variant of Knight's Landing was never offered to the general market and was discontinued by August 2017. This included the 7220A, 7240P and 7220P coprocessor cards. Intel announced they were discontinuing Knights Landing in summer 2018.
Models All models can boost to their peak speeds, adding 200 MHz to their base frequency when running just one or two cores. When running from three to the maximum number of cores, the chips can only boost 100 MHz above the base frequency. All chips run high-AVX code at a frequency reduced by 200 MHz.
Knights Mill Knights Mill is Intel's codename for a Xeon Phi product specialized in
deep learning, initially released in December 2017. Nearly identical in specifications to Knights Landing, Knights Mill includes optimizations for better utilization of AVX-512 instructions. Single-precision and variable-precision floating-point performance increased, at the expense of double-precision floating-point performance.
Models Knights Hill Knights Hill was the codename for the third-generation MIC architecture, for which Intel announced the first details at SC14. It was to be manufactured in a 10 nm process. Knights Hill was expected to be used in the
United States Department of Energy Aurora supercomputer, to be deployed at
Argonne National Laboratory. However, Aurora was delayed in favor of using an "advanced architecture" with a focus on machine learning. In 2017, Intel announced that Knights Hill had been canceled in favor of another architecture built from the ground up to enable
Exascale computing in the future. This new architecture was expected for 2020–2021; however, this was also cancelled due to the discontinuation of the Xeon Phi. ==Programming==