Contemporary FPGAs have ample
logic gates and RAM blocks to implement complex digital computations. FPGAs can be used to implement any logical function that an
ASIC can perform. The ability to update the functionality after shipping,
partial re-configuration of a portion of the design and the low non-recurring engineering costs relative to an ASIC design (notwithstanding the generally higher unit cost), offer advantages for many applications. As FPGA designs employ very fast I/O rates and bidirectional data
buses, it becomes a challenge to verify correct timing of valid data within setup time and hold time.
Floor planning helps resource allocation within FPGAs to meet these timing constraints. Some FPGAs have analog features in addition to digital functions. The most common analog feature is a programmable
slew rate on each output pin. This allows the user to set low rates on lightly loaded pins that would otherwise
ring or
couple unacceptably, and to set higher rates on heavily loaded high-speed channels that would otherwise run too slowly. Also common are quartz-
crystal oscillator driver circuitry, on-chip
RC oscillators, and
phase-locked loops with embedded
voltage-controlled oscillators used for clock generation and management as well as for high-speed serializer and deserializer (SERDES) transmit clocks and receiver clock recovery. Fairly common are differential
comparators on input pins designed to be connected to
differential signaling channels. A few
mixed-signal FPGAs have integrated peripheral
analog-to-digital converters (ADCs) and
digital-to-analog converters (DACs) with analog signal conditioning blocks, allowing them to operate as a
system on a chip (SoC). Such devices blur the line between an FPGA, which carries digital ones and zeros on its internal programmable interconnect fabric, and
field-programmable analog array (FPAA), which carries analog values on its internal programmable interconnect fabric.
Logic blocks , FA –
full adder, DFF –
D-type flip-flop) The most common FPGA architecture consists of an array of
logic blocks called configurable logic blocks (CLBs) or logic array blocks (LABs) (depending on vendor),
I/O pads, and routing channels. In general, a logic block consists of a few logical cells. A typical cell consists of a 4-input LUT, a
full adder (FA) and a
D-type flip-flop. The LUT might be split into two 3-input LUTs. In
normal mode those are combined into a 4-input LUT through the first
multiplexer (mux). In
arithmetic mode, their outputs are fed to the adder. The selection of mode is programmed into the second mux. The output can be either
synchronous or
asynchronous, depending on the programming of the third mux. In practice, the entire adder or parts of it are
stored as functions into the LUTs in order to save
space.
Hard blocks Modern FPGA families expand upon the above capabilities to include higher-level functionality fixed in silicon. Having these common functions embedded in the circuit reduces the area required and gives those functions increased performance compared to building them from logical primitives. Examples of these include
multipliers, generic
DSP blocks,
embedded processors, high-speed I/O logic and embedded
memories. Higher-end FPGAs can contain high-speed
multi-gigabit transceivers and
hard IP cores such as
processor cores,
Ethernet medium access control units,
PCI or
PCI Express controllers, and external
memory controllers. These cores exist alongside the programmable fabric, but they are built out of
transistors instead of LUTs so they have ASIC-level performance and power consumption without consuming a significant amount of fabric resources, leaving more of the fabric free for the application-specific logic. The multi-gigabit transceivers also contain high-performance
signal conditioning circuitry along with high-speed serializers and deserializers, components that cannot be built out of LUTs. Higher-level physical layer (PHY) functionality such as
line coding may or may not be implemented alongside the serializers and deserializers in hard logic, depending on the FPGA.
Soft core Zynq-7000 all-programmable system on a chip An alternate approach to using hard macro processors is to make use of
soft processor IP cores that are implemented within the FPGA logic.
Nios II,
MicroBlaze and
Mico32 are examples of popular softcore processors. Many modern FPGAs are programmed at
run time, which has led to the idea of
reconfigurable computing or reconfigurable systems –
CPUs that reconfigure themselves to suit the task at hand. Additionally, new non-FPGA architectures are beginning to emerge. Software-configurable microprocessors such as the Stretch S5000 adopt a hybrid approach by providing an array of processor cores and FPGA-like programmable cores on the same chip.
Integration In 2012 the coarse-grained architectural approach was taken a step further by combining the
logic blocks and interconnects of traditional FPGAs with embedded
microprocessors and related peripherals to form a complete
system on a programmable chip. Examples of such hybrid technologies can be found in the
Xilinx Zynq-7000 all
programmable SoC, which includes a 1.0
GHz dual-core
ARM Cortex-A9 MPCore processor
embedded within the FPGA's logic fabric, or in the
Altera Arria V FPGA, which includes an 800 MHz
dual-core ARM Cortex-A9 MPCore. The
Atmel FPSLIC is another such device, which uses an
AVR processor in combination with Atmel's programmable logic architecture. The
Microsemi SmartFusion devices incorporate an ARM Cortex-M3 hard processor core (with up to 512 kB of
flash and 64 kB of RAM) and analog
peripherals such as a multi-channel
analog-to-digital converters and
digital-to-analog converters in their
flash memory-based FPGA fabric.
Clocking Most of the logic inside of an FPGA is
synchronous circuitry that requires a
clock signal. FPGAs contain dedicated global and regional routing networks for clock and reset, typically implemented as an
H tree, so they can be delivered with minimal
skew. FPGAs may contain analog
phase-locked loop or
delay-locked loop components to synthesize new
clock frequencies and manage
jitter. Complex designs can use multiple clocks with different frequency and phase relationships, each forming separate
clock domains. These clock signals can be generated locally by an oscillator or they can be recovered from a
data stream. Care must be taken when building
clock domain crossing circuitry to avoid
metastability. Some FPGAs contain
dual port RAM blocks that are capable of working with different clocks, aiding in the construction of building
FIFOs and dual port buffers that bridge clock domains.
3D architectures To shrink the size and power consumption of FPGAs, vendors such as
Tabula and
Xilinx have introduced
3D or stacked architectures. Following the introduction of its
28 nm 7-series FPGAs, Xilinx said that several of the highest-density parts in those FPGA product lines will be constructed using multiple dies in one package, employing technology developed for 3D construction and stacked-die assemblies. Xilinx's approach stacks several (three or four) active FPGA dies side by side on a silicon
interposer – a single piece of silicon that carries passive interconnect. The multi-die construction also allows different parts of the FPGA to be created with different process technologies, as the process requirements are different between the FPGA fabric itself and the very high speed serial transceivers. An FPGA built in this way is called a
heterogeneous FPGA. Altera's heterogeneous approach involves using a single monolithic FPGA die and connecting other dies and technologies to the FPGA using Intel's embedded multi-die interconnect bridge (EMIB) technology. == Programming ==