MIPS architecture processors

MIPS, showing the five stages: instruction fetch, instruction decode, execute, memory access and write back. The first MIPS microprocessor, the R2000, was announced in 1985. It added multiple-cycle multiply and divide instructions in a somewhat independent on-chip unit. New instructions were added to retrieve the results from this unit back to the processor register file; these result-retrieving instructions were interlocked. The R2000 could be booted either big-endian or little-endian. It had thirty-one 32-bit general purpose registers, but no status register (condition code register (CCR), the designers considered it a potential bottleneck), a feature it shares with the AMD 29000, the DEC Alpha, and RISC-V. Unlike other registers, the program counter is not directly accessible. The R2000 also had support for up to four co-processors, one of which was built into the main central processing unit (CPU) and handled exceptions, traps and memory management, while the other three were left for other uses. One of these could be filled by the optional R2010 floating-point unit (FPU), which had thirty-two 32-bit registers that could be used as sixteen 64-bit registers for double-precision. The R3000 succeeded the R2000 in 1988, adding 32 KB (soon raised to 64 KB) caches for instructions and data, and support for shared-memory multiprocessing in the form of a cache coherence protocol. While there were flaws in the R3000s multiprocessing support, it was successfully used in several successful multiprocessor computers. The R3000 also included a built-in memory management unit (MMU), a common feature on CPUs of the era. The R3000, like the R2000, could be paired with a R3010 FPU. The R3000 was the first successful MIPS design in the market, and eventually over one million were made. A faster version of the R3000 running up to 40 MHz, the R3000A delivered a performance of 32 million instructions per second (MIPS), or VAX Unit of Performance (VUPs). The MIPS R3000A-compatible R3051 running at 33.8688 MHz was the processor used in the Sony PlayStation though it didn't have FPU or MMU. Third-party designs include Performance Semiconductor's R3400 and IDT's R3500, both of them were R3000As with an integrated R3010 FPU. Toshiba's R3900 was a virtually first system on a chip (SoC) for the early handheld PCs that ran Windows CE. A radiation-hardened variant for outer space use, the Mongoose-V, is a R3000 with an integrated R3010 FPU. The R4000 series, released in 1991, extended MIPS to a full 64-bit word design, moved the FPU onto the main die to form a single-chip microprocessor, and had a then high clock rate of 100 MHz at introduction. However, to achieve the clock frequency, the caches were reduced to 8 KB each and they took three cycles to access. The high clock rates were achieved through the method of deep pipelining (called super-pipelining then). The improved R4400 followed in 1993. It had larger 16 KB primary caches, largely bug-free 64-bit operation, and support for a larger L2 cache. MIPS, now a division of Silicon Graphics (SGI) named MTI, designed the low-cost R4200, the basis for the even cheaper R4300i. A derivative of this microprocessor, the NEC VR4300, was used in the Nintendo 64 game console. , designed by Quantum Effect Devices Orion Quantum Effect Devices (QED), a separate company started by former MIPS employees, designed the R4600 Orion, the R4700 Orion, the R4650 and the R5000. Where the R4000 had pushed clock frequency and sacrificed cache capacity, the QED designs emphasized large caches which could be accessed in just two cycles and efficient use of silicon area. The R4600 and R4700 were used in low-cost versions of the SGI Indy workstation as well as the first MIPS-based Cisco routers, such as the 36x0 and 7x00-series routers. The R4650 was used in the original WebTV set-top boxes (now Microsoft TV). The R5000 FPU had more flexible single precision floating-point scheduling than the R4000, and as a result, R5000-based SGI Indys had much better graphics performance than similarly clocked R4400 Indys with the same graphics hardware. SGI gave the old graphics board a new name when it was combined with R5000, to emphasize the improvement. QED later designed the RM7000 and RM9000 family of devices for embedded system markets like computer networking and laser printers. QED was acquired by the semiconductor manufacturer PMC-Sierra in August 2000, the latter company continuing to invest in the MIPS architecture. The RM7000 included an integrated 256 KB L2 cache and a controller for optional L3 cache. The RM9xx0 were a family of SOC devices which included northbridge peripherals such as memory controller, PCI controller, Gigabit Ethernet controller and fast I/O such as a HyperTransport port. The R8000 (1994) was the first superscalar MIPS design, able to execute two integer or floating point and two memory instructions per cycle. The design was spread over six chips: an integer unit (with 16 KB instruction and 16 KB data caches), a floating-point unit, three fully-custom secondary cache tag RAMs (two for secondary cache accesses, one for bus snooping), and a cache controller ASIC. The design had two fully pipelined double precision multiply-add units, which could stream data from the 4 MB off-chip secondary cache. The R8000 powered SGI's POWER Challenge servers in the mid-1990s and later became available in the POWER Indigo2 workstation. Although its FPU performance fit scientific users quite well, its limited integer performance and high cost dampened appeal for most users. The R8000 was sold for only a year and remains fairly rare. In 1995, the R10000 was released. This processor was a single-chip design, ran at a higher clock frequency than the R8000, and had larger 32 KB primary instruction and data caches. It was also superscalar, but its major innovation was out-of-order execution. Even with one memory pipeline and simpler FPU, the vastly improved integer performance, lower price, and higher density made the R10000 preferable for most customers. Some later designs have been based upon R10000 core. The R12000 used a 0.25 micrometre process to shrink the chip and achieve higher clock rates. The revised R14000 allowed higher clock rates with added support for double data rate synchronous dynamic random-access memory (DDR SDRAM) static random access memory (SRAM) in the off-chip cache. Later iterations are named R16000 and R16000A, and feature higher clock rates and smaller die manufacturing compared with before. Other members of the MIPS family include the R6000, an emitter-coupled logic (ECL) implementation produced by Bipolar Integrated Technology. The R6000 introduced the MIPS II architecture. Its translation lookaside buffer (TLB) and cache architecture are different from all other members of the MIPS family. The R6000 did not deliver the promised performance benefits, and although it saw some use in Control Data machines, it quickly disappeared from the mainstream market. == History ==