Chiplet packaging For the first time ever in a consumer GPU, RDNA 3 utilizes modular
chiplets rather than a single large monolithic
die. AMD previously had great success with its use of chiplets in its
Ryzen desktop and
Epyc server processors. The decision to move to a chiplet-based GPU microarchitecture was led by AMD Senior Vice President
Sam Naffziger who had also lead the chiplet initiative with Ryzen and Epyc. The development of RDNA 3's chiplet architecture began towards the end of 2017 with Naffziger leading the AMD graphics team in the effort. The benefit of using chiplets is that dies can be
fabricated on different process nodes depending on their functions and intended purpose. According to Naffziger, cache and SRAM do not scale as linearly as logic does on advanced nodes like N5 in terms of density and power consumption so they can instead be fabricated on the cheaper, more mature N6 node. The use of smaller dies rather than one large monolithic die is beneficial for maximizing wafer yields as more dies can be fitted onto a single wafer. An organic package could not host the number of wires that would be needed to connect multiple dies in a GPU. data RDNA 3's dies are instead connected using
TSMC's Integrated Fan-Out Re-Distribution Layer (InFO-RDL) packaging technique which provides a silicon bridge for high bandwidth and high density die-to-die communication. InFO allows dies to be connected without the use of a more costly silicon
interposer such as the one used in AMD's Instinct MI200 and MI300 datacenter accelerators. Each Infinity Fanout link has 9.2 Gbps in bandwidth. Naffziger explains that "The bandwidth density that we achieve is almost 10x" with the Infinity Fanout rather than the wires used by Ryzen and Epyc processors. The chiplet interconnects in RDNA achieve cumulative bandwidth of 5.3TB/s. Also present on each MCD are two physical 32-bit GDDR6 memory interfaces for a combined 64-bit interface per MCD. The Radeon RX 7900 XTX has a 384-bit memory bus through the use of six MCDs while the RX 7900 XT has a 320-bit bus due to its five MCDs.
Graphics Compute Die (GCD) Compute Units RDNA 3's Compute Units (CUs) for graphics processing are organized in dual CU Work Group Processors (WGPs). Rather than including a very large number of WGPs in RDNA 3 GPUs, AMD instead focused on improving per-WGP throughput. This is done with improved
dual-issue shader ALUs with the ability to execute two instructions per cycle. It can contain up to 96 graphics Compute Units that can provide up to 61 TFLOPS of compute. While RDNA 3 include dedicated execution units for AI acceleration like the Matrix Cores found in AMD's compute-focused
CDNA architectures, the efficiency of running inference tasks on
FP16 execution resources is improved with Wave MMA (
matrix multiply–accumulate) instructions. This results in increased inference performance compared to RDNA 2. WMMA supports FP16, BF16, INT8, and INT4 data types. ''
Tom's Hardware'' found that AMD's fastest RDNA 3 GPU, the RX 7900 XTX, was capable of generating 26 images per minute with
Stable Diffusion, compared to only 6.6 images per minute of the RX 6950 XT, the fastest RDNA 2 GPU.
Ray tracing RDNA 3 features second generation ray-tracing accelerators. Each Compute Unit contains one ray tracing accelerator. The overall number of ray tracing accelerators is increased due to the higher number of Compute Units, though the number of ray tracing accelerators per Compute Unit has not increased over RDNA 2.
Clock speeds RDNA 3 was designed to support high clock speeds. On RDNA 3, clock speeds have been decoupled with the front end operating at a 2.5GHz frequency while the shaders operate at 2.3GHz. The shaders operating at a lower clock speed gives up to 25% power savings according to AMD and RDNA 3's shader clock speed is still 15% faster than RDNA 2.
Cache and memory subsystem RDNA 3 increased the capacity of L1 and L2 caches. The 16-way associative L1 cache shared across a shader array is doubled in RDNA 3 to 256KB. The L2 cache increased from 4MB on
RDNA 2 to 6MB on RDNA 3. The L3 Infinity Cache has been lowered in capacity from 128MB to 96MB and latency has increased as it is physically present on the MCDs rather than being closer to the WGPs within the GCD. The Infinity Cache capacity was decreased due to RDNA 3 having wider a memory interface up to 384-bit whereas RDNA 2 used memory interfaces up to 256-bit. RDNA 3 having a wider 384-bit memory means that its cache hitrate does not have to be as high to still avoid bandwidth bottlenecks as there is higher memory bandwidth. AMD's AMF
AV1 encoder is comparable in quality to Nvidia's
NVENC AV1 encoder but can handle a higher number of simultaneous encoding streams compared to the limit of 3 on the
GeForce RTX 40 series.
Display engine RDNA 3 GPUs feature a new display engine called the "Radiance Display Engine". AMD touted its support for
DisplayPort 2.1 UHBR 13.5, delivering up to 54Gbps bandwidth for high refresh rates at
4K and
8K resolutions. The Radeon Pro W7900 and W7800 support the 80Gbps UHBR20 standard. DisplayPort 2.1 can support 4K at 480Hz and 8K at 165Hz with
Display Stream Compression (DSC). The previous DisplayPort 1.4 standard with DSC was limited to 4K at 240Hz and 8K at 60Hz.
Power efficiency AMD claims that RDNA 3 achieves a 54% increase in performance-per-watt which is in line with their previous claims of 50% performance-per-watt increases for both RDNA and RDNA 2. == Navi 3x dies ==