I2C patents and specifications used the terms
master/slave between 1980 and 2021. The technical definitions of such devices, and their roles on an I2C bus, remain unchanged. Common I2C bus speeds are the
standard mode and the
fast mode. There is also a
low-speed mode, but arbitrarily low clock frequencies are also allowed. Later revisions of I2C can host more nodes and run at faster speeds (
fast mode,
fast mode plus,
high-speed mode, and
ultra-fast mode). These speeds are more widely used on embedded systems than on PCs. Note that the bit rates are quoted for the transfers between controller (master) and target (slave) without clock stretching or other hardware overhead. Protocol overheads include a target address and perhaps a register address within the target device, as well as per-byte ACK/NACK bits. Thus the actual transfer rate of user data is lower than those peak bit rates alone would imply. For example, if each interaction with a target inefficiently allows only 1 byte of data to be transferred, the data rate will be less than half the peak bit rate. The number of nodes that can exist on a given I2C bus is limited by the address space and also by the total bus
capacitance of 400
pF, which restricts practical communication distances to a few meters. The relatively high impedance and low noise immunity require a common ground potential, which again restricts practical use to communication within the same PC board or small system of boards.
Reference design The aforementioned reference design is a bus with a
clock (SCL) and data (SDA) lines with 7-bit addressing. The bus has two roles for nodes, either controller (master) or target (slave): • Controller (master) node: Node that generates the clock and initiates communication with targets (slaves). • Target (slave) node: Node that receives the clock and responds when addressed by the controller (master). The bus is a multi-controller bus, which means that any number of controller nodes can be present. Additionally, controller and target roles may be changed between messages (after a STOP is sent). There may be four potential modes of operation for a given bus device, although most devices only use a single role and its two modes: • Controller (master) transmit: Controller node is sending data to a target (slave). • Controller (master) receive: Controller node is receiving data from a target (slave). • Target (slave) transmit: Target node is sending data to the controller (master). • Target (slave) receive: Target node is receiving data from the controller (master). In addition to 0 and 1 data bits, the I2C bus allows special START and STOP signals, which act as message delimiters and are distinct from the data bits. (This is in contrast to the
start bits and
stop bits used in
asynchronous serial communication, which are distinguished from data bits only by their timing.) The controller is initially in controller transmit mode by sending a START followed by the 7-bit address of the target it wishes to communicate with, which is finally followed by a single bit representing whether it wishes to write (0) to or read (1) from the target. If the target exists on the bus then it will respond with an
ACK bit (active low for acknowledged) for that address. The controller then continues in either transmit or receive mode (according to the read/write bit it sent), and the target continues in the complementary mode (receive or transmit, respectively). The address and the data bytes are sent
most significant bit first. The start condition is indicated by a high-to-low transition of SDA with SCL high; the stop condition is indicated by a low-to-high transition of SDA with SCL high. All other transitions of SDA take place with SCL low. If the controller wishes to write to the target, then it repeatedly sends a byte with the target sending an ACK bit. (In this situation, the controller is in controller transmit mode, and the target is in target receive mode.) If the controller wishes to read from the target, then it repeatedly receives a byte from the target, the controller sending an ACK bit after every byte except the last one. (In this situation, the controller is in controller receive mode, and the target is in target transmit mode.) An I2C transaction may consist of multiple messages. The controller terminates a message with a STOP condition if this is the end of the transaction or it may send another START condition to retain control of the bus for another message (a "combined format" transaction).
Message protocols I2C defines basic types of transactions, each of which begins with a START and ends with a STOP: • Single message where a controller (master) writes data to a target (slave). • Single message where a controller (master) reads data from a target (slave). • Combined format, where a controller (master) issues at least two reads or writes to one or more targets (slaves). In a combined transaction, each read or write begins with a START and the target address. The START conditions after the first are also called
repeated START bits. Repeated STARTs are not preceded by STOP conditions, which is how targets know that the next message is part of the same transaction. Any given target will only respond to certain messages, as specified in its product documentation. Pure I2C systems support arbitrary message structures.
SMBus is restricted to nine of those structures, such as
read word N and
write word N, involving a single target.
PMBus extends SMBus with a
Group protocol, allowing multiple such SMBus transactions to be sent in one combined message. The terminating STOP indicates when those grouped actions should take effect. For example, one PMBus operation might reconfigure three power supplies (using three different I2C target addresses), and their new configurations would take effect at the same time: when they receive that STOP. With only a few exceptions, neither I2C nor SMBus define message semantics, such as the meaning of data bytes in messages. Message semantics are otherwise product-specific. Those exceptions include messages addressed to the I2C
general call address (0x00) or to the SMBus
Alert Response Address; and messages involved in the SMBus
Address Resolution Protocol (ARP) for dynamic address allocation and management. In practice, most targets adopt request-response control models, where one or more bytes following a write command are treated as a command or address. Those bytes determine how subsequent written bytes are treated or how the target responds on subsequent reads. Most SMBus operations involve single-byte commands.
Messaging example: 24C32 EEPROM M24C08-BN6: serial
EEPROM with I2C bus One specific example is the 24C32 type
EEPROM, which uses two request bytes that are called Address High and Address Low. (Accordingly, these EEPROMs are not usable by pure SMBus hosts, which support only single-byte commands or addresses.) These bytes are used for addressing bytes within the 32
kbit (or 4
kB) EEPROM address space. The same two-byte addressing is also used by larger EEPROMs, like the 24C512, which stores 512 kbits (or 64 kB). Writing data to and reading from these EEPROMs uses a simple protocol: the address is written, and then data is transferred until the end of the message. The data transfer part of the protocol can cause trouble on the SMBus, since the data bytes are not preceded by a count, and more than 32 bytes can be transferred at once. I2C EEPROMs smaller than 32 kbit, like the 2 kbit 24C02, are often used on the SMBus with inefficient single-byte data transfers to overcome this problem. A single message writes to the EEPROM. After the START, the controller sends the chip's bus address with the direction bit clear (
write), then sends the two-byte address of data within the EEPROM and then sends data bytes to be written starting at that address, followed by a STOP. When writing multiple bytes, all the bytes must be in the same 32-byte page. While it is busy saving those bytes to memory, the EEPROM will not respond to further I2C requests. (That is another incompatibility with SMBus: SMBus devices must always respond to their bus addresses.) To read starting at a particular address in the EEPROM, a combined message is used. After a START, the controller first writes that chip's bus address with the direction bit clear (
write) and then the two bytes of EEPROM data address. It then sends a (repeated) START and the EEPROM's bus address with the direction bit set (
read). The EEPROM will then respond with the data bytes beginning at the specified EEPROM data address — a combined message: first a write, then a read. The controller issues an ACK after each read byte except the last byte, and then issues a STOP. The EEPROM increments the address after each data byte transferred; multi-byte reads can retrieve the entire contents of the EEPROM using one combined message.
Physical layer s where a transmission error would only cause an inconsequential brief visual
glitch. The resemblance to other I2C bus modes is limited to: • the start and stop conditions are used to delimit transfers, • I2C addressing allows multiple target devices to share the bus without
SPI bus style target select signals, and • a ninth clock pulse is sent per byte transmitted, marking the position of the unused acknowledgement bits. Some of the vendors provide a so-called non-standard
Turbo mode with a speed up to . In all modes, the clock frequency is controlled by the controller(s), and a longer-than-normal bus may be operated at a slower-than-nominal speed by
underclocking.
Circuit interconnections board with I2C interface I2C is popular for interfacing peripheral circuits to prototyping systems, such as the
Arduino and
Raspberry Pi. I2C does not employ a standardized connector; however, board designers have created various wiring schemes for I2C interconnections. To minimize the possible damage due to plugging 0.1-inch headers in backwards, some developers have suggested using alternating signal and power connections of the following wiring schemes: (GND, SCL, VCC, SDA) or (VCC, SDA, GND, SCL). The vast majority of applications use I2C in the way it was originally designed—peripheral ICs directly wired to a processor on the same printed circuit board, and therefore over relatively short distances of less than , without a connector. However using a differential driver, an alternate version of I2C can communicate up to 20 meters (possibly over 100 meters) over
CAT5 or other cable. Several standard connectors carry I2C signals. For example, the
UEXT, the 10-pin iPack, and the
6P6C Lego Mindstorms NXT connectors carry I2C. Every
HDMI and most
DVI and
VGA connectors carry
DDC2 data over I2C. Additionally,
8P8C connectors and a
CAT5 cable normally used for the
Ethernet physical layer can sometimes be used to carry differential-encoded or boosted single-ended I2C signals.
Buffering and multiplexing When there are many I2C devices in a system, there can be a need to include bus
buffers or
multiplexers to split large bus segments into smaller ones. This can be necessary to keep the capacitance of a bus segment below the allowable value or to allow multiple devices with the same address to be separated by a multiplexer. Many types of multiplexers and buffers exist and all must take into account the fact that I2C lines are specified to be bidirectional. Multiplexers can be implemented with analog switches, which can tie one segment to another. Analog switches maintain the bidirectional nature of the lines but do not isolate the capacitance of one segment from another or provide buffering capability. Buffers can be used to isolate capacitance on one segment from another and/or allow I2C to be sent over longer cables or traces. Buffers for bi-directional lines such as I2C must use one of several schemes for preventing latch-up. I2C is open-drain, so buffers must drive a low on one side when they see a low on the other. One method for preventing latch-up is for a buffer to have carefully selected input and output levels such that the output level of its driver is higher than its input threshold, preventing it from triggering itself. For example, a buffer may have an input threshold of 0.4 V for detecting a low, but an output low level of 0.5 V. This method requires that all other devices on the bus have thresholds which are compatible and often means that multiple buffers implementing this scheme cannot be put in series with one another. Alternatively, other types of buffers exist that implement current amplifiers or keep track of the state (i.e., which side drove the bus low) to prevent latch-up. The state method typically means that an unintended pulse is created during a hand-off when one side is driving the bus low, then the other drives it low, then the first side releases (this is common during an I2C acknowledgement).
Sharing SCL between multiple buses When having a single controller, it is possible to have multiple I2C buses share the same SCL line. The packets on each bus are either sent one after the other or at the same time. This is possible because the communication on each bus can be subdivided into alternating short periods with high SCL followed by short periods with low SCL. And the clock can be stretched if one bus needs more time in one state. Advantages are using target devices with the same address at the same time and saving connections or a faster throughput by using several data lines at the same time.
Line state table These tables show the various atomic states and bit operations that may occur during an I2C message.
Addressing structure 7-bit addressing 10-bit addressing Reserved addresses in 7-bit address space Two groups of 8 addresses each are reserved for special functions: • From: 0000 000 to 0000 111 • From: 1111 000 to 1111 111 In addition, the remaining 112 addresses are designated for specific classes of devices, and some of them are further reserved by either related standards or common usage. SMBus reserves some additional addresses. In particular, 0001 000 is reserved for the SMBus host, which may be used by controller-capable devices, 0001 100 is the "SMBus alert response address" which is polled by the host after an out-of-band interrupt, and 1100 001 is the default address which is initially used by devices capable of dynamic address assignment.
Non-reserved addresses in 7-bit address space Although MSB 1111 is reserved for Device ID and 10-bit target (slave) addressing, it is also used by VESA
DDC display dependent devices such as
pointing devices.
Transaction format An I2C
transaction consists of one or more
messages. Each message begins with a start symbol, and the transaction ends with a stop symbol. Start symbols after the first, which begin a message but not a transaction, are referred to as
repeated start symbols. Each message is a read or a write. A transaction consisting of a single message is called either a read or a write transaction. A transaction consisting of multiple messages is called a combined transaction. The most common form of the latter is a write message providing intra-device address information, followed by a read message. Many I2C devices do not distinguish between a combined transaction and the same messages sent as separate transactions, but not all. The device ID protocol requires a single transaction; targets are forbidden from responding if they observe a stop symbol. Configuration, calibration or self-test modes that cause the target to respond unusually are also often automatically terminated at the end of a transaction.
Timing diagram • Data transfer is initiated with a
start condition (S) signalled by SDA being pulled low while SCL stays high. • SCL is pulled low, and SDA sets the first data bit level while keeping SCL low (during blue bar time). • The data is sampled (received) when SCL rises for the first bit (B1). For a bit to be valid, SDA must not change between a rising edge of SCL and the subsequent falling edge (the entire green bar time). • This process repeats, SDA transitioning while SCL is low, and the data being read while SCL is high (B2 through Bn). • The final bit is followed by a clock pulse, during which SDA is pulled low in preparation for the
stop bit. • A
stop condition (P) is signalled when SCL rises, followed by SDA rising. To avoid false marker detection, there is a minimum delay between the SCL falling edge and changing SDA, and between changing SDA and the SCL rising edge. The minimum delay time is dependent upon the data transfer rate in use. Note that an I2C message containing data bits (including acknowledgements) contains clock pulses.
Software Design I2C lends itself to a "bus driver" software design. Software for attached devices is written to call a "bus driver" that handles the actual low-level I2C hardware. This permits the driver code for attached devices to port easily to other hardware, including a bit-banging design. == Operating system support ==