Xeon

The Xeon brand has been maintained over several generations of IA-32 and x86-64 processors. The P6-based models added the Xeon moniker to the end of the name of their corresponding desktop processor, but all models since 2001 used the name Xeon on its own. The Xeon CPUs generally have more cache and cores than their desktop counterparts in addition to multiprocessing capabilities. Xeon Scalable The Xeon Scalable brand for high-performance server was introduced in May 2017 with the Skylake-based Xeon Platinum 8100 series. Xeon Scalable processors range from dual socket to 8 socket support. Within the Xeon Scalable brand, there exists the hierarchy of Xeon Bronze, Silver, Gold and Platinum. In April 2024, Intel announced at its Vision event that the Xeon Scalable brand would be retired, beginning with 6th generation Xeon processors codenamed Sierra Forest and Granite Rapids that will now be referred to as "Xeon 6" processors. This change brings greater emphasis on processor generation numbers. Xeon 6 With the launch of Intel's Sierra Forest line of processors, branding for mainstream server processors switched to Xeon #, with the # being the generation of the processor, such as Xeon 6 for the 6th generation of Xeon processors, this naming convention also carries over to the Granite Rapids line of server CPUs. Xeon 6 is split into two product lines, the E series and P series, which, respectively, are all E core and all P core designs. For example, the Xeon 6 6700E line is an all E core based (Sierra Forest) line of processors. It was announced in 2014 and the first Xeon D processors were released in March 2015. Xeon D processors come in an soldered BGA package rather than in a socketable form factor. Xeon D was introduced to compete with emerging ARM hyperscale server solutions that offered greater multi-threaded performance and power efficiency. Early 2025, the Xeon 6 SoC line was announced as the 'next gen' for at least a part of the Xeon D lineup. Xeon W Xeon W branding is used for Xeon workstation processors. It was first introduced in August 2017 with the release of the Skylake-based Xeon W-2100 series workstation processors. With Sapphire Rapids-WS workstation processors that launched in March 2023, Intel introduced tiers within Xeon W. Xeon w3, w5, w7 and w9 was designed to emulate the Core i3, i5, i7 and i9 branding that Intel had been using for its desktop processors. == Overview ==

Some shortcomings that make Xeon processors unsuitable for most consumer-grade desktop PCs include lower clock rates at the same price point (since servers run more tasks in parallel than desktops, core counts are more important than clock rates), and, usually, the lack of an integrated graphics processing unit (GPU). Processor models prior to Sapphire Rapids-WS lack support for overclocking (with the exception of Xeon W-3175X). Despite such disadvantages, Xeon processors have always had popularity among some desktop users (video editors and other power users), mainly due to higher core count potential, and higher performance to price ratio vs. the Core i7 in terms of total computing power of all cores. Since most Intel Xeon CPUs lack an integrated GPU, systems built with those processors require a discrete graphics card or a separate GPU if computer monitor output is desired. Intel Xeon is a distinct product line from the similarly named Intel Xeon Phi. The first-generation Xeon Phi is a completely different type of device more comparable to a graphics card; it is designed for a PCI Express slot and is meant to be used as a multi-core coprocessor, like the Nvidia Tesla. In the second generation, Xeon Phi evolved into a main processor more similar to the Xeon. It conforms to the same socket as a Xeon processor and is x86-compatible; however, as compared to Xeon, the design point of the Xeon Phi emphasizes more cores with higher memory bandwidth. ==P6-based Xeon==

Pentium II Xeon The first Xeon-branded processor was the Pentium II Xeon (code-named "Drake"). It was released in 1998, replacing the Pentium Pro in Intel's high-end server lineup. The Pentium II Xeon was a "Deschutes" Pentium II (and shared the same product code: 80523) with a full-speed 512 kB (1 kB = 1024 B), 1 MB (1 MB = 1024 kB = 10242 B), or 2 MB L2 cache. The L2 cache was implemented with custom 512 kB SRAMs developed by Intel. The number of SRAMs depended on the amount of cache. A 512 kB configuration required one SRAM, a 1 MB configuration: two SRAMs, and a 2 MB configuration: four SRAMs on both sides of the PCB. Each SRAM was a 12.90 mm by 17.23 mm (222.21 mm) die fabricated in a 0.35 μm four-layer metal CMOS process and packaged in a cavity-down wire-bonded land grid array (LGA). The additional cache required a larger module and thus the Pentium II Xeon used a larger slot, Slot 2. It was supported by the i440GX dual-processor workstation chipset and the i450NX quad- or octo-processor server chipset. Pentium III Xeon In 1999, the Pentium II Xeon was replaced by the Pentium III Xeon. Reflecting the incremental changes from the Pentium II "Deschutes" core to the Pentium III "Katmai" core, the first Pentium III Xeon, named "Tanner", was just like its predecessor except for the addition of Streaming SIMD Extensions (SSE) and a few cache controller improvements. The product codes for Tanner mirrored that of Katmai; 80525. The second version, named "Cascades", was based on the Pentium III "Coppermine" core. The "Cascades" Xeon used a 133 MT/s front side bus and relatively small 256 kB on-die L2 cache resulting in almost the same capabilities as the Slot 1 Coppermine processors, which were capable of dual-processor operation but not quad-processor or octa-processor operation. To improve this situation, Intel released another version, officially also named "Cascades", but often referred to as "Cascades 2 MB". That came in two variants: with 1 MB or 2 MB of L2 cache. Its bus speed was fixed at 100 MT/s, though in practice the cache was able to offset this. The product code for Cascades mirrored that of Coppermine; 80526. == NetBurst-based Xeon ==

Xeon (DP) and Xeon MP (32-bit) Foster In mid-2001, the Xeon brand was introduced ("Pentium" was dropped from the name). The initial variant that used the new NetBurst microarchitecture, "Foster", was slightly different from the desktop Pentium 4 ("Willamette"). It was a decent chip for workstations, but for server applications it was almost always outperformed by the older Cascades cores with a 2 MB L2 cache and AMD's Athlon MP. Combined with the need to use expensive Rambus Dynamic RAM, the Foster's sales were somewhat unimpressive. At most two Foster processors could be accommodated in a symmetric multiprocessing (SMP) system built with a mainstream chipset, so a second version (Foster MP) was introduced with 512 KB or 1 MB L3 cache and the Jackson Hyper-Threading capacity. This improved performance slightly, but not enough to lift it out of third place. It was also priced much higher than the dual-processor (DP) versions. The Foster shared the 80528 product code with Willamette. Prestonia In 2002, Intel released a 130 nm version of Xeon branded CPU, codenamed "Prestonia". It supported Intel's new Hyper-Threading technology and had a 512 kB L2 cache. This was based on the "Northwood" Pentium 4 core. A new server chipset, E7500 (which allowed the use of dual-channel DDR SDRAM), was released to support this processor in servers, and soon the bus speed was boosted to 533 MT/s (accompanied by a new socket and two new chipsets: the E7501 for servers and the E7505 for workstations). The Prestonia performed much better than its predecessor and noticeably better than Athlon MP. The support of new features in the E75xx series also gave it a key advantage over the Pentium III Xeon and Athlon MP branded CPUs (both stuck with rather old chipsets), and it quickly became the top-selling server/workstation processor. Gallatin Subsequent to the Prestonia was the "Gallatin", which had an L3 cache of 1 MB or 2 MB. Its Xeon MP version, which succeeded Foster MP, was popular in servers. Later experience with the 130 nm process allowed Intel to create the Xeon MP branded Gallatin with 4 MB cache. The Xeon branded Prestonia and Gallatin were designated 80532, like Northwood. Xeon (DP) and Xeon MP (64-bit) Nocona and Irwindale Due to a lack of success with Intel's Itanium and Itanium 2 processors, AMD was able to introduce x86-64, a 64-bit extension to the x86 architecture. Intel followed suit by including Intel 64 (formerly EM64T; it is almost identical to AMD64) in the 90 nm version of the Pentium 4 ("Prescott"), and a Xeon version codenamed "Nocona" with 1 MB L2 cache was released in 2004. Released with it were the E7525 (workstation), E7520 and E7320 (both server) chipsets, which added support for PCI Express 1.0a, DDR2 and Serial ATA 1.0a. The Xeon was noticeably slower than AMD's Opteron, although it could be faster in situations where Hyper-Threading came into play. A slightly updated core called "Irwindale" was released in early 2005, with 2 MB L2 cache and the ability to have its clock speed reduced during low processor demand. Although it was a bit more competitive than the Nocona had been, independent tests showed that AMD's Opteron still outperformed Irwindale. Both of these Prescott-derived Xeons have the product code 80546. Cranford and Potomac 64-bit Xeon MPs were introduced in April 2005. The cheaper "Cranford" was an MP version of Nocona, while the more expensive "Potomac" was a Cranford with 8 MB of L3 cache. Like Nocona and Irwindale, they also have product code 80546. Dual-Core Xeon "Paxville DP" The first dual-core CPU branded Xeon, codenamed Paxville DP, product code 80551, was released by Intel on October 10, 2005. Paxville DP had NetBurst microarchitecture, and was a dual-core equivalent of the single-core Irwindale (related to the Pentium D branded "Smithfield") with 4 MB of L2 cache (2 MB per core). The only Paxville DP model released ran at 2.8 GHz, featured an 800 MT/s front side bus, and was produced using a 90 nm process. 7000-series "Paxville MP" An MP-capable version of Paxville, codenamed Paxville MP, product code 80560, was released on November 1, 2005. There are two versions: one with 2 MB of L2 cache (1 MB per core), and one with 4 MB of L2 (2 MB per core). Paxville MP, called the dual-core Xeon 7000-series, was produced using a 90 nm process. Paxville MP clock ranges between 2.67 GHz and 3.0 GHz (model numbers 7020–7041), with some models having a 667 MT/s FSB, and others having an 800 MT/s FSB. 7100-series "Tulsa" Released on August 29, 2006, the 7100 series, codenamed Tulsa (product code 80550), is an improved version of Paxville MP, built on a 65 nm process, with 2 MB of L2 cache (1 MB per core) and up to 16 MB of L3 cache. It uses Socket 604. Tulsa was released in two lines: the N-line uses a 667 MT/s FSB, and the M-line uses an 800 MT/s FSB. The N-line ranges from 2.5 GHz to 3.5 GHz (model numbers 7110N-7150N), and the M-line ranges from 2.6 GHz to 3.4 GHz (model numbers 7110M-7140M). L3 cache ranges from 4 MB to 16 MB across the models. 5000-series "Dempsey" On May 23, 2006, Intel released the dual-core CPU (Xeon branded 5000 series) codenamed Dempsey (product code 80555). Released as the Dual-Core Xeon 5000-series, Dempsey is a NetBurst microarchitecture processor produced using a 65 nm process, and is virtually identical to Intel's "Presler" Pentium Extreme Edition, except for the addition of SMP support, which lets Dempsey operate in dual-processor systems. Dempsey ranges between 2.50 GHz and 3.73 GHz (model numbers 5020–5080). Some models have a 667 MT/s FSB, and others have a 1066 MT/s FSB. Dempsey has 4 MB of L2 cache (2 MB per core). A Medium Voltage model, at 3.2 GHz and 1066 MT/s FSB (model number 5063), has also been released. Dempsey also introduces a new interface for Xeon processors: LGA 771, also known as Socket J. Dempsey was the first Xeon core in a long time to be somewhat competitive with its Opteron-based counterparts, although it could not claim a decisive lead in any performance metric – that would have to wait for its successor, the Woodcrest. == Pentium M (Yonah) based Xeon ==

LV (ULV), "Sossaman" On March 14, 2006, Intel released a dual-core processor codenamed Sossaman and branded as Xeon LV (low-voltage). Subsequently, an ULV (ultra-low-voltage) version was released. The Sossaman was a low-/ultra-low-power and double-processor capable CPU (like AMD Quad FX), based on the "Yonah" processor, for ultradense non-consumer environment (i.e., targeted at the blade-server and embedded markets), and was rated at a thermal design power (TDP) of 31 W (LV: 1.66 GHz, 2 GHz and 2.16 GHz) and 15 W (ULV: 1.66 GHz). As such, it supported most of the same features as earlier Xeons: Virtualization Technology, 667 MT/s front side bus, and dual-core processing, but did not support 64-bit operations, so it could not run 64-bit server software, such as Microsoft Exchange Server 2007, and therefore was limited to 16 GB of memory. A planned successor, codenamed "Merom MP" was to be a drop-in upgrade to enable Sossaman-based servers to upgrade to 64-bit capability. However, this was abandoned in favor of low-voltage versions of the Woodcrest LV processor leaving the Sossaman at a dead-end with no upgrade path. == Core-based Xeon ==

Dual-Core 3000-series "Conroe" The 3000 series, codenamed Conroe (product code 80557) dual-core Xeon (branded) CPU, released at the end of September 2006, was the first Xeon for single-CPU operation and is designed for entry-level uniprocessor servers. The same processor is branded as Core 2 Duo or as Pentium Dual-Core and Celeron, with varying features disabled. They use LGA 775 (Socket T), operate on a 1066 MT/s front-side bus, support Enhanced Intel SpeedStep Technology and Intel Virtualization Technology but do not support hyper-threading. Conroe processors with a number ending in "5" have a 1333 MT/s FSB. • Models marked with an asterisk (*) are not present in Intel's Ark database. 3100-series "Wolfdale" The 3100 series, codenamed Wolfdale (product code 80570) dual-core Xeon (branded) CPU, was just a rebranded version of the Intel's mainstream Core 2 Duo E7000/E8000 and Pentium Dual-Core E5000 processors, featuring the same 45 nm process and 6 MB of L2 cache. Unlike most Xeon processors, they only support single-CPU operation. They use LGA 775 (Socket T), operate on a 1333 MT/s front-side bus, support Enhanced Intel SpeedStep Technology and Intel Virtualization Technology but do not support Hyper-Threading. 5100-series "Woodcrest" {{Infobox CPU On June 26, 2006, Intel released the dual-core CPU (Xeon branded 5100 series) codenamed Woodcrest (product code 80556); it was the first Intel Core/Merom microarchitecture processor to be launched on the market. It is a dual-processor server and workstation version of the Core 2 processor. Intel claimed that it provides an 80% boost in performance, while reducing power consumption by 20% relative to the 5000 series Dempsey. Most models have a 1333MT/s FSB, except for the 5110 and 5120, which have a 1066MT/s FSB. The fastest processor (5160) operates at 3.0GHz. All Woodcrest processors use the LGA 771 (Socket J) socket and all except two models have a TDP of 65W. The 5160 has a TDP of 80W and the 5148LV (2.33GHz) has a TDP of 40W. The previous generation Xeons had a TDP of 130W. All models support Intel 64 (Intel's x86-64 implementation), the XD bit, and Virtualization Technology, with the Demand-based switching power management option only on Dual-Core Xeon 5140 or above. Woodcrest has 4 MB of shared L2 cache. 5200-series "Wolfdale-DP" On November 11, 2007, Intel released the dual-core CPU (Xeon branded 5200 series) codenamed Wolfdale-DP (product code 80573). It is built on a 45 nm process like the desktop Core 2 Duo and Xeon Wolfdale, featuring Intel 64 (Intel's x86-64 implementation), the XD bit, and Virtualization Technology. It is unclear whether the Demand-based switching power management is available on the L5238. Wolfdale has 6 MB of shared L2 cache. 7200-series "Tigerton" The 7200 series, codenamed Tigerton (product code 80564) is an MP-capable processor, similar to the 7300 series, but, in contrast, there is a single dual-core die. Quad-Core and Six-Core Xeon 3200-series "Kentsfield " Intel released rebranded versions of its quad-core (2×2) Core 2 Quad processor as the Xeon 3200-series (product code 80562) on January 7, 2007. The 2 × 2 "quad-core" (dual-die dual-core) comprised two separate dual-core die next to each other in one CPU package. The models are the X3210, X3220 and X3230, running at 2.13 GHz, 2.4 GHz and 2.66 GHz, respectively. Like the 3000-series, these models only support single-CPU operation and operate on a 1066 MT/s front-side bus. It is targeted at the "blade" market. The X3220 is also branded and sold as Core2 Quad Q6600, the X3230 as Q6700. 3300-series "Yorkfield" Intel released relabeled versions of its quad-core Core 2 Quad Yorkfield Q9300, Q9400, Q9x50 and QX9770 processors as the Xeon 3300-series (product code 80569). This processor comprises two separate dual-core dies next to each other in one CPU package and manufactured in a 45 nm process. The models are the X3320, X3330, X3350, X3360, X3370 and X3380, being rebadged Q9300, Q9400, Q9450, Q9550, Q9650, QX9770, running at 2.50 GHz, 2.66 GHz, 2.66 GHz, 2.83 GHz, 3.0 GHz, and 3.16 GHz, respectively. The L2 cache is a unified 6 MB per die (except for the X3320 and X3330 with a smaller 3 MB L2 cache per die), and a front-side bus of 1333 MHz. All models feature Intel 64 (Intel's x86-64 implementation), the XD bit, and Virtualization Technology, as well as Demand-based switching. The Yorkfield-CL (product code 80584) variant of these processors are X3323, X3353 and X3363. They have a reduced TDP of 80W and are made for single-CPU LGA 771 systems instead of LGA 775, which is used in all other Yorkfield processors. In all other respects, they are identical to their Yorkfield counterparts. 5300-series "Clovertown" A quad-core (2×2) successor of the Woodcrest for DP segment, consisting of two dual-core Woodcrest chips in one package similarly to the dual-core Pentium D branded CPUs (two single-core chips) or the quad-core Kentsfield. All Clovertowns use the LGA 771 package. The Clovertown has been usually implemented with two Woodcrest dies on a multi-chip module, with 8 MB of L2 cache (4 MB per die). Like Woodcrest, lower models use a 1066 MT/s FSB, and higher models use a 1333 MT/s FSB. Intel released Clovertown, product code 80563, on November 14, 2006 with models E5310, E5320, E5335, E5345, and X5355, ranging from 1.6 GHz to 2.66 GHz. All models support MMX, SSE, SSE2, SSE3, SSSE3, Intel 64, XD bit (an NX bit implementation), Intel VT. The E and X designations are borrowed from Intel's Core 2 model numbering scheme; an ending of -0 implies a 1066 MT/s FSB, and an ending of -5 implies a 1333 MT/s FSB. on April 4, 2007. The X5365 performs up to around 38 GFLOPS in the LINPACK benchmark. 5400-series "Harpertown" On November 11, 2007 Intel presented Yorkfield-based Xeons – called Harpertown (product code 80574) – to the public. This family consists of dual die quad-core CPUs manufactured on a 45 nm process and featuring 1066 MHz, 1333 MHz, 1600 MHz front-side buses, with TDP rated from 40 W to 150 W depending on the model. These processors fit in the LGA 771 package. All models feature Intel 64 (Intel's x86-64 implementation), the XD bit, and Virtualization Technology. All except the E5405 and L5408 also feature Demand-based switching. The supplementary character in front of the model-number represents the thermal rating: an L depicts a TDP of 40 W or 50 W, an E depicts 80 W whereas an X is 120 W TDP or above. The speed of 3.00 GHz comes as four models, two models with 80 W TDP two other models with 120 W TDP with 1333 MHz or 1600 MHz front-side bus respectively. The fastest Harpertown is the X5492 whose TDP of 150 W is higher than those of the Prescott-based Xeon DP but having twice as many cores. (The X5482 is also sold under the name "Core 2 Extreme QX9775" for use in the Intel Skulltrail system.) Intel 1.6 GT/s front-side bus Xeon processors will drop into the Intel 5400 (Seaburg) chipset whereas several mainboards featuring the Intel 5000/5200-chipset are enabled to run the processors with a 1333 MHz front-side bus speed. Seaburg features support for dual slots and up to 128 GB of memory. 7300-series "Tigerton QC" The 7300 series, codenamed Tigerton QC (product code 80565) is a four-socket (packaged in Socket 604) and more capable quad-core processor, consisting of two dual core Core 2 architecture silicon chips on a single ceramic module, similar to Intel's Xeon 5300 series Clovertown processor modules. The 7300 series uses Intel's Caneland (Clarksboro) platform. Intel claims the 7300 series Xeons offer more than twice the performance per watt as Intel's previous generation 7100 series. The 7300 series' Caneland chipset provides a point to point interface allowing the full front side bus bandwidth per processor. The 7xxx series is aimed at the large server market, supporting configurations of up to 32 CPUs per host. 7400-series "Dunnington" Dunnington – the last CPU of the Penryn generation and Intel's first multi-core (above two) die – features a single-die six- (or hexa-) core design with three unified 3 MB L2 caches (resembling three merged 45 nm dual-core Wolfdale-3M dies), and 96 kB L1 cache (Data) and 16 MB of L3 cache. It features a 1.07 GT/s FSB, fits into the Tigerton's mPGA604 socket, and is compatible with both the Intel Caneland and IBM X4 chipsets. These processors support DDR2-1066 (533 MHz), and have a maximum TDP below 130 W. They are intended for blades and other stacked computer systems. Availability was scheduled for the second half of 2008. It was followed shortly by the Nehalem microarchitecture. Total transistor count is 1.9 billion. Announced on September 15, 2008. == Nehalem-based Xeon ==

3400-series "Lynnfield" Xeon 3400-series processors based on Lynnfield are designed for entry-level servers compared to Bloomfield, which is designed for uniprocessor workstations. Like Bloomfield, they are quad-core single-package processors based on the Nehalem microarchitecture, but were introduced almost a year later, in September 2009. The same processors are marketed for mid-range to high-end desktops systems as Core i5 and Core i7. They have two integrated memory channels as well as PCI Express and Direct Media Interface (DMI) links, but no QuickPath Interconnect (QPI) interface. 3400-series "Clarkdale" At low end of the 3400-series is not a Lynnfield but a Clarkdale processor, which is also used in the Core i3-500 and Core i5-600 processors as well as the Celeron G1000 and G6000 Pentium series. A single model was released in March 2010, the Xeon L3406. Compared to all other Clarkdale-based products, this one does not support integrated graphics, but has a much lower thermal design power of just 30 W. Compared to the Lynnfield-based Xeon 3400 models, it only offers two cores. W3500-series "Bloomfield" Bloomfield (or Nehalem-E) is the codename for the successor to the Xeon 3300 series, is based on the Nehalem microarchitecture and uses the same 45 nm manufacturing methods as Intel's Penryn. The first processor released with the Nehalem architecture is the high-end desktop Core i7, which was released in November 2008. This is the server version for single CPU systems. This is a single-socket Intel Xeon processor designed for uniprocessor workstations. The performance improvements over the previous Xeon 3300 series are based mainly on: • Integrated memory controller supporting three memory channels of DDR3 UDIMM (Unbuffered) or RDIMM (Registered) • A new point-to-point processor interconnect QuickPath, replacing the legacy front side bus • Simultaneous multithreading by multiple cores and hyper-threading (2× per core). • Turbo Boost, an overclocking technology that allows the CPU to run at a clock speed higher than the base speed as needed 5500-series "Gainestown" Gainestown or Nehalem-EP (Efficient Performance), the successor to Wolfdale-DP, and Harpertown, is based on the Nehalem microarchitecture and uses the same 45 nm manufacturing methods. The first processor released with the Nehalem microarchitecture is the high-end desktop Core i7, which was released in November 2008. Server processors of the Xeon 55xx range were first supplied to testers in December 2008. The performance improvements over Wolfdale-DP and Harpertown processors are based mainly on: • Monolithic design for quad-core models • Integrated memory controller supporting three memory channels of DDR3 memory with ECC support. • A new point-to-point processor interconnect QuickPath, replacing the legacy front side bus. Gainestown has two QuickPath interfaces. • Hyper-threading (2× per core, starting from 5518), that was already present in NetBurst-based processors • Turbo Boost, an overclocking technology that allows the CPU to run at a clock speed higher than the base speed as needed C3500/C5500-series "Jasper Forest" Jasper Forest is a Nehalem-based embedded processor with PCI Express connections on-die, core counts from 1 to 4 cores and power envelopes from 23 to 85 watts. The uni-processor version without QPI comes as LC35xx and EC35xx, while the dual-processor version is sold as LC55xx and EC55xx and uses QPI for communication between the processors. Both versions use a DMI link to communicate with the 3420 that is also used in the 3400-series Lynfield Xeon processors, but use an LGA 1366 package that is otherwise used for processors with QPI but no DMI or PCI Express links. The CPUID code of both Lynnfield and Jasper forest is 106Ex, i.e., family 6, model 30. The Celeron P1053 belongs into the same family as the LC35xx series, but lacks some RAS features that are present in the Xeon version. W3600/5600-series "Gulftown" & "Westmere-EP" Gulftown and Westmere-EP, six-core 32 nm architecture Westmere-based processors, are the basis for the Xeon 36xx and 56xx series and the Core i7-980X. It launched in the first quarter of 2010. The 36xx-series follows the 35xx-series Bloomfield uni-processor model while the 56xx-series follows the 55xx-series Gainestown dual-processor model and both are socket compatible to their predecessors. 6500/7500-series "Beckton" {{Infobox CPU Beckton or Nehalem-EX (Expandable server market) is a Nehalem-based processor with up to eight cores and uses buffering inside the chipset to support up to 16 standard DDR3 DIMMs per CPU socket without requiring the use of FB-DIMMs. Unlike all previous Xeon MP processors, Nehalem-EX uses the new LGA 1567 (Socket LS) package, replacing the Socket 604 used in the previous models, up to Xeon 7400 "Dunnington". The 75xx models have four QuickPath interfaces, so it can be used in up-to eight-socket configurations, while the 65xx models are only for up to two sockets. Designed by the Digital Enterprise Group (DEG) Santa Clara and Hudson Design Teams, Beckton is manufactured on the P1266 (45 nm) technology. Its launch in March 2010 coincided with that of its direct competitor, AMD's Opteron 6xxx "Magny-Cours". Most models limit the number of cores and QPI links as well as the L3 cache size in order to get a broader range of products out of the single chip design. E7-x8xx-series "Westmere-EX" Westmere-EX is the follow-on to Beckton/Nehalem-EX and the first Intel processor to have ten CPU cores. The microarchitecture is the same as in the six-core Gulftown/Westmere-EP processor, but it uses the LGA 1567 package like Beckton to support up to eight sockets. Starting with Westmere-EX, the naming scheme has changed once again, with "E7-xxxx" now signifying the high-end line of Xeon processors using a package that supports larger than two-CPU configurations, formerly the 7xxx series. Similarly, the 3xxx uniprocessor and 5xxx dual-processor series turned into E3-xxxx and E5-xxxx, respectively, for later processors. ==Sandy Bridge- and Ivy Bridge-based Xeon==

E3-12xx-series "Sandy Bridge" The Xeon E3-12xx line of processors, introduced in April 2011, uses the Sandy Bridge chips that are also the base for the Core i3/i5/i7-2xxx and Celeron/Pentium Gxxx products using the same LGA 1155 socket, but with a different set of features disabled. Notably, the Xeon variants include support for ECC memory, VT-d and trusted execution that are not present on the consumer models, while only some Xeon E3 enable the integrated GPU that is present on Sandy Bridge. Like its Xeon 3400-series predecessors, the Xeon E3 only supports operation with a single CPU socket and is targeted at entry-level workstations and servers. The CPUID of this processor is 0206A7h, the product code is 80623. E3-12xx v2-series "Ivy Bridge" Xeon E3-12xx v2 is a minor update of the Sandy Bridge-based E3-12xx, using the 22 nm shrink, and providing slightly better performance while remaining backwards compatible. They were released in May 2012 and mirror the desktop Core i3/i5/i7-3xxx parts. E5-14xx/24xx series "Sandy Bridge-EN" and E5-16xx/26xx/46xx-series "Sandy Bridge-EP" The Xeon E5-16xx processors follow the previous Xeon 3500/3600-series products as the high-end single-socket platform, using the LGA 2011 package introduced with this processor. They share the Sandy Bridge-E platform with the single-socket Core i7-38xx and i7-39xx processors. The CPU chips have no integrated GPU but eight CPU cores, some of which are disabled in the entry-level products. The Xeon E5-26xx line has the same features but also enables multi-socket operation like the earlier Xeon 5000-series and Xeon 7000-series processors. E5-14xx v2/24xx v2 series "Ivy Bridge-EN" and E5-16xx v2/26xx v2/46xx v2 series "Ivy Bridge-EP" The Xeon E5 v2 line was an update, released in September 2013 to replace the original Xeon E5 processors with a variant based on the Ivy Bridge shrink. The maximum number of CPU cores was raised to 12 per processor module and the total L3 cache was upped to 30 MB. The consumer version of the Xeon E5-16xx v2 processor is the Core i7-48xx and 49xx. E7-28xx v2/48xx v2/88xx v2 series "Ivy Bridge-EX" The Xeon E7 v2 line was an update, released in February 2014 to replace the original Xeon E7 processors with a variant based on the Ivy Bridge shrink. There was no Sandy Bridge version of these processors but rather a Westmere version. == Haswell-based Xeon ==

E3-12xx v3 series "Haswell-WS" Introduced in May 2013, Xeon E3-12xx v3 is the first Xeon series based on the Haswell microarchitecture. It uses the new LGA 1150 socket, which was introduced with the desktop Core i5/i7 Haswell processors, incompatible with the LGA 1155 that was used in Xeon E3 and E3 v2. As before, the main difference between the desktop and server versions is added support for ECC memory in the Xeon-branded parts. The main benefit of the new microarchitecture is better power efficiency. E5-16xx/26xx v3 series "Haswell-EP" Introduced in September 2014, Xeon E5-16xx v3 and Xeon E5-26xx v3 series use the new LGA 2011-v3 socket, which is incompatible with the LGA 2011 socket used by earlier Xeon E5 and E5 v2 generations based on Sandy Bridge and Ivy Bridge microarchitectures. Some of the main benefits of this generation, compared to the previous one, are improved power efficiency, higher core counts, and bigger last level caches (LLCs). Following the already used nomenclature, Xeon E5-26xx v3 series allows dual-socket operation. One of the new features of this generation is that Xeon E5 v3 models with more than 10 cores support cluster on die (COD) operation mode, allowing CPU's multiple columns of cores and LLC slices to be logically divided into what is presented as two non-uniform memory access (NUMA) CPUs to the operating system. By keeping data and instructions local to the "partition" of CPU which is processing them, thus decreasing the LLC access latency, COD brings performance improvements to NUMA-aware operating systems and applications. E7-48xx/88xx v3 series "Haswell-EX" Introduced in May 2015, Xeon E7-48xx v3 and Xeon E7-88xx v3 series provide higher core counts, higher per-core performance and improved reliability features, compared to the previous Xeon E7 v2 generation. Following the usual SKU nomenclature, Xeon E7-48xx v3 and E7-88xx v3 series allow multi-socket operation, supporting up to quad- and eight-socket configurations, respectively. These processors use the LGA 2011 (R1) socket. Xeon E7-48xx v3 and E7-88xx v3 series contain a quad-channel integrated memory controller (IMC), supporting both DDR3 and DDR4 LRDIMM or RDIMM memory modules through the use of Jordan Creek (DDR3) or Jordan Creek 2 (DDR4) memory buffer chips. Both versions of the memory buffer chip connect to the processor using version 2.0 of the Intel Scalable Memory Interconnect (SMI) interface, while supporting lockstep memory layouts for improved reliability. Up to four memory buffer chips can be connected to a processor, with up to six DIMM slots supported per each memory buffer chip. == Broadwell-based Xeon ==

E3-12xx v4 series "Broadwell-H" Introduced in June 2015, Xeon E3-12xx v4 is the first Xeon series based on the Broadwell microarchitecture. It uses LGA 1150 socket, which was introduced with the desktop Core i5/i7 Haswell processors. As before, the main difference between the desktop and server versions is added support for ECC memory in the Xeon-branded parts. The main benefit of the new microarchitecture is the new lithography process, which results in better power efficiency. == Skylake-based Xeon ==

E3-12xx v5 series "Skylake-S" Introduced in October 2015, Xeon E3-12xx v5 is the first Xeon series based on the Skylake microarchitecture. It uses new LGA 1151 socket, which was introduced with the desktop Core i5/i7 Skylake processors. Although it uses the same socket as consumer processors, it is limited to the C200 server chipset series and will not work with consumer chipsets like Z170. As before, the main difference between the desktop and server versions is added support for ECC memory in the Xeon-branded parts. == Kaby Lake-based Xeon ==

E3-12xx v6 series Introduced in January 2017, Xeon E3-12xx v6 is the first Xeon series based on the Kaby Lake microarchitecture. It uses the same LGA 1151 socket, which was introduced with the desktop Core i5/i7 Kaby Lake processors. As before, the main difference between the desktop and server versions is added support for ECC memory and improved energy efficiency in the Xeon-branded parts. == Coffee Lake-based Xeon ==

Coffee Lake-E (Server/Workstation) Coffee Lake-E Refresh (Server/Workstation) == Comet Lake-based Xeon ==

Variants • Server: Cascade Lake-SP (Scalable Performance; meaning multi physical processors configuration), Cascade Lake-AP (Advanced Performance) • Workstation: Cascade Lake-W • Enthusiast: Cascade Lake-X == Cooper Lake-based Xeon ==

The 3rd generation Xeon SP processors for 4S and 8S. == Ice Lake-based Xeon ==

The 3rd generation Xeon SP processors for WS, 1S and 2S. == Rocket Lake-based Xeon ==

== Sapphire Rapids-based Xeon ==

Introduced in 2023, the 4th generation Xeon Scalable processors (Sapphire Rapids-SP and Sapphire Rapids-HBM) and Xeon W-2400 and W-3400 series (Sapphire Rapids-WS) provide large performance enhancements over the prior generation. Variants • Server: Sapphire Rapids-SP (Scalable Performance; meaning multi physical processors configuration), Sapphire Rapids-AP (Advanced Performance) • Enthusiast/High End Desktop: Sapphire Rapids-W Features CPU • Up to 60 Golden Cove CPU cores per package • AVX512-FP16 • TSX Suspend Load Address Tracking (TSXLDTRK) • Advanced Matrix Extensions (AMX) • Trust Domain Extensions (TDX), a collection of technologies to help deploy hardware-isolated virtual machines (VMs) called trust domains (TDs) Accelerators • In-Field Scan (IFS), a technology that allows for testing the processor for potential hardware faults without taking it completely offline • Data Streaming Accelerator (DSA), an ASIC allows for speeding up data copy and transformation between different kinds of storage • QuickAssist Technology (QAT), an ASIC allows for improved performance of compression and encryption tasks • Dynamic Load Balancer (DLB), an ASIC allows for offloading tasks of load balancing, packet prioritization and queue management • In-Memory Analytics Accelerator (IAA), an ASIC allows accelerating in-memory databases and big data analytics Not all accelerators are available in all processor models. Some accelerators are available under the Intel On Demand program, also known as Software Defined Silicon (SDSi), where a license is required to activate a given accelerator that is physically present in the processor. The license can be obtained as a one-time purchase or as a paid subscription. Activating the license requires support in the operating system. A driver with the necessary support was added in Linux kernel version 6.2. I/O • PCI Express 5.0 • Direct Media Interface 4.0 • 8-channel DDR5 memory support up to DDR5-4800, up to 2 DIMMs per channel • On-package High Bandwidth Memory 2e memory as L4 cache on Xeon Max models • Compute Express Link 1.1 == Emerald Rapids-based Xeon ==

== Granite Rapids-based Xeon ==

== Diamond Rapids-based Xeon ==